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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Vector computer memory bank contention

A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips or else feature very large numbers of independent memory banks.

Bailey, David H.↗
NASA NTRS2006

Programs for Testing Processor-in-Memory Computing Systems

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.]

Katz, Daniel S.↗
NASA NTRS1995

Nonlinear structural analysis on distributed-memory computers

A computational strategy is presented for the nonlinear static and postbuckling analyses of large complex structures on massively parallel computers. The strategy is designed for distributed-memory, message-passing parallel computer systems. The key elements of the proposed strategy are: (1) a multiple-parameter reduced basis technique; (2) a nested dissection (or multilevel substructuring) ordering scheme; (3) parallel assembly of global matrices; and (4) a parallel sparse equation solver. The effectiveness of the strategy is assessed by applying it to thermo-mechanical postbuckling analyses of stiffened composite panels with cutouts, and nonlinear large-deflection analyses of HSCT models on Intel Paragon XP/S computers. The numerical studies presented demonstrate the advantages of nested dissection-based solvers over traditional skyline-based solvers on distributed memory machines.

Watson, Brian C.↗
NASA NTRS1972

An adaptive replacement algorithm for paged-memory computer systems.

A general class of adaptive replacement schemes for use in paged memories is developed. One such algorithm, called SIM, is simulated using a probability model that generates memory traces, and the results of the simulation of this adaptive scheme are compared with those obtained using the best nonlookahead algorithms. A technique for implementing this type of adaptive replacement algorithm with state of the art digital hardware is also presented.

Thorington, J. M., Jr.↗
NASA NTRS1997

Distributed-Memory Computing With the Langley Aerothermodynamic Upwind Relaxation Algorithm (LAURA)

The Langley Aerothermodynamic Upwind Relaxation Algorithm (LAURA), a Navier-Stokes solver, has been modified for use in a parallel, distributed-memory environment using the Message-Passing Interface (MPI) standard. A standard domain decomposition strategy is used in which the computational domain is divided into subdomains with each subdomain assigned to a processor. Performance is examined on dedicated parallel machines and a network of desktop workstations. The effect of domain decomposition and frequency of boundary updates on performance and convergence is also examined for several realistic configurations and conditions typical of large-scale computational fluid dynamic analysis.

Riley, Christopher J.↗
NASA NTRS1993

Multiple-User, Multitasking, Virtual-Memory Computer System

Computer system designed and programmed to serve multiple users in research laboratory. Provides for computer control and monitoring of laboratory instruments, acquisition and anlaysis of data from those instruments, and interaction with users via remote terminals. System provides fast access to shared central processing units and associated large (from megabytes to gigabytes) memories. Underlying concept of system also applicable to monitoring and control of industrial processes.

Generazio, Edward R.↗
NASA NTRS1971

A study of nitride devices for computer memory applications

Metal-nitride-oxide-silicon /MNOS/ capacitors act like metal-nitride-silicon /MNS/ capacitors with extra interface where sheet of charge can be stored in slow states. Flatband voltage shifts over a wide range by adjusting store charge density.

Raburn, W. D.↗
NASA NTRS1980

Conserving power in computer memories

Power control system for electronic memories saves energy by switching off power to portions of memories that are not in use. Although power-off period lasts only a few microseconds or milliseconds, it amounts to sizable part of overall read/write cycle timer; large energy savings can be realized.

Source record↗
NASA NTRS1979

Simulation of cosmic-ray induced soft errors and latchup in integrated-circuit computer memories

Soft errors have been induced in solid-state static RAM's by iron nuclei from the Lawrence Berkeley Laboratory (LBL) Bevalac, in experiments designed to prove the ability of iron-group cosmic rays to generate such errors. Subsequently, various delidded device types were tested in beams of argon and krypton ions from the LBL 88-inch Cyclotron, at energies near 2 MeV/nucleon. The latter tests showed that some devices are essentially immune to bit error while others are quite susceptible. Good agreement was obtained with model predictions in cases where the latter exist. Latchup, whose cause is attributed to individual heavy ions, was also observed in some device types.

Kolasinski, W. A.↗
NASA NTRS1984

Reed Solomon codes for error control in byte organized computer memory systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Lin, S.↗
NASA NTRS1985

Low-Voltage Protection For Volatile Computer Memories

Short-circuit current provides minimum memory power. Protective circuit includes dc-to-dc converter that supplies keep-alive voltage to memories when short circuit occurs in any of system loads. Converter powered by lowvoltage across two of three series diodes generated by short-circuit bus current. Relay switch is in open (short-circuit-detected) position. Protective circuit useful wherever necessary to improve reliability of volatile memories or other circuits that must not lose power.

Detwiler, R. C.↗
NASA NTRS1993

Solid-state Isotopic Power Source for Computer Memory Chips

Recent developments in materials technology now make it possible to fabricate nonthermal thin-film radioisotopic energy converters (REC) with a specific power of 24 W/kg and a 10 year working life at 5 to 10 watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25 percent which is two to three times greater than the 6 to 8 percent capabilities of current thermoelectric systems. Radio isotopic energy converters have the potential to meet many future space power requirements for a wide variety of applications with less mass, better efficiency, and less total area than other power conversion options. These benefits result in significant dollar savings over the projected mission lifetime.

Brown, Paul M.↗
NASA NTRS1994

Parallel grid generation algorithm for distributed memory computers

A parallel grid-generation algorithm and its implementation on the Intel iPSC/860 computer are described. The grid-generation scheme is based on an algebraic formulation of homotopic relations. Methods for utilizing the inherent parallelism of the grid-generation scheme are described, and implementation of multiple levELs of parallelism on multiple instruction multiple data machines are indicated. The algorithm is capable of providing near orthogonality and spacing control at solid boundaries while requiring minimal interprocessor communications. Results obtained on the Intel hypercube for a blended wing-body configuration are used to demonstrate the effectiveness of the algorithm. Fortran implementations bAsed on the native programming model of the iPSC/860 computer and the Express system of software tools are reported. Computational gains in execution time speed-up ratios are given.

Moitra, Stuti↗
NASA NTRS1994

Equation solvers for distributed-memory computers

A large number of scientific and engineering problems require the rapid solution of large systems of simultaneous equations. The performance of parallel computers in this area now dwarfs traditional vector computers by nearly an order of magnitude. This talk describes the major issues involved in parallel equation solvers with particular emphasis on the Intel Paragon, IBM SP-1 and SP-2 processors.

Storaasli, Olaf O.↗
NASA NTRS1994

Rapid solution of large-scale systems of equations

The analysis and design of complex aerospace structures requires the rapid solution of large systems of linear and nonlinear equations, eigenvalue extraction for buckling, vibration and flutter modes, structural optimization and design sensitivity calculation. Computers with multiple processors and vector capabilities can offer substantial computational advantages over traditional scalar computer for these analyses. These computers fall into two categories: shared memory computers and distributed memory computers. This presentation covers general-purpose, highly efficient algorithms for generation/assembly or element matrices, solution of systems of linear and nonlinear equations, eigenvalue and design sensitivity analysis and optimization. All algorithms are coded in FORTRAN for shared memory computers and many are adapted to distributed memory computers. The capability and numerical performance of these algorithms will be addressed.

Storaasli, Olaf O.↗