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DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗

DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗

DOE OSTI2025

Testing of Novel Semiconductor Opening Switches Using Magnetic Switching

The performance of semiconductor opening switch (SOS) diodes with different doping profiles is assessed with the primary aim of enhancing or substituting hard-to-find devices. SOS devices are capable of providing long lifetime, gigawatt level pulses in generators with risetimes on the nanosecond scale with pulse widths on the order of 20 ns. An experimental testbed is described which allows for rapid testing of diodes with control of the forward pumping time which is a crucial parameter of SOS diodes. A saturable pulse transformer provides both the initial voltage multiplication and reverse current pulse required to drive SOS diodes. Voltage multiplication ratios of 16:1 were achieved with a modest charging voltage of 800 V and simple circuitry. With current densities of up to 1.4 kA ⋅ cm -2 , the testbed produces 10 kV output pulses into a 56 Ω load with a pulsewidth of 16 ns and delivered power of up to 1.9 MW. These novel devices are compared to legacy SOS diodes originating from Russia, with one of the profiles yielding increased performance. Finally, these profiles are studied in hopes of creating manufacturing demand to augment the availability of these useful devices.

drift step recovery diodes↗

DOE OSTI2025

Intermodal microwave-to-optical transduction using silicon-on-sapphire optomechanical ring resonator

Optomechanical and electro-optomechanical systems have emerged as one of the most promising approaches for quantum microwave-to-optical transduction to interconnect distributed quantum modalities for scaling the quantum systems. These systems use suspended structures to increase mode overlap and mitigate loss to achieve high efficiency. However, the suspended design’s poor heat dissipation under strong drive limits the ultimate efficiency. Here, we demonstrate an unsuspended optomechanical ring resonator (OMR) based on the silicon-on-sapphire (SOS) platform for microwave-to-optical frequency conversion. The OMR achieves a triply resonant optical-to-optical conversion with an enhanced coupling rateG b = 3.6 gigahertz per square-root milliwatt at a peak conversion efficiency of 1.2% with 3.6-milliwatt microwave drive power and a microwave-to-optical conversion efficiency of 1.5 × 10 −5 at 10-milliwatt optical drive power. Our results show that the unsuspended SOS platform, which mitigates the thermal effect and is compatible with superconducting qubits, is a promising platform for optomechanical circuitry and quantum transduction.

Science & Technology - Other Topics↗

DOE OSTI2025

Cryogenic thermal modeling of microwave high density signaling

Superconducting quantum computers require microwave control lines running from room temperature to the mixing chamber of a dilution refrigerator. Adding more lines without preliminary thermal modeling to make predictions risks overwhelming the cooling power at each thermal stage. In this paper, we investigate the thermal load of SC-086/50-SCN-CN semi-rigid coaxial cable, which is commonly used for the control and readout lines of a superconducting quantum computer, as we increase the number of lines to a quantum processor. We investigate the makeup of the coaxial cables, verify the materials and dimensions, and experimentally measure the total thermal conductivity of a single cable as a function of the temperature from cryogenic to room temperature values. We also measure the cryogenic DC electrical resistance of the inner conductor as a function of temperature, allowing for the calculation of active thermal loads due to Ohmic heating. Fitting this data produces a numerical thermal conductivity function used to calculate the static heat loads due to thermal transfer within the wires resulting from a temperature gradient. The resistivity data is used to calculate active heat loads, and we use these fits in a cryogenic model of a superconducting quantum processor in a typical Bluefors XLD1000-SL dilution refrigerator, investigating how the thermal load increases with processor sizes ranging from 100 to 225 qubits. We conclude that the theoretical upper limit of the described architecture is approximately 200 qubits. However, including an engineering margin in the cooling power and the available space for microwave readout circuitry at the mixing chamber, the practical limit is approximately 140 qubits.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗

DOE OSTI2024

Exascale-Enabled Models and Algorithms for Microelectronics Applications (MicroEleX) v1

The MicroEleX code package contains a variety of models and algorithms for physical modeling of microelectronic circuitry, including electrostatics, electrodynamics, superconducting physics, micromagnetics, multi-ferroic systems, and quantum transport. MicroEleX leverages the AMReX software framework to provide scalability on GPU-based supercomputing architectures. The code is open source and designed to be algorithmically flexible so developers can incorporate enhanced or customized physics.

Nonaka, Andy↗

DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗

DOE OSTI2024

Material and Interface Engineering Strategies to Mitigate Decoherence in Superconducting Qubits

While significant strides have been made to increase the coherence time of superconducting qubits, further advancements are essential for realizing scalable quantum computing. Decoherence is often a result of loss and noise stemming from two-level systems and excess quasiparticles, arising due to material defects, fabrication processes, and ambient exposure, particularly at surfaces and interfaces. Our recent efforts to mitigate these decoherence mechanisms have employed a variety of strategies, including low-loss surface encapsulation materials, advanced substrate preparation techniques, modifications to metal film growth, and the development of novel fabrication processes. The structural and chemical properties of materials, surfaces, and interfaces are studied using scanning probe microscopy, electron microscopy, photoelectron spectroscopy, mass spectrometry, and X-ray diffraction, which is correlated to device performance metrics, including superconducting resonator internal quality factor and qubit T1 time. This information is used to identify and understand material sources of loss and their origins in the device fabrication process. Through multi-institution efforts within SQMS we have identified the loss mechanism of interstitial hydrogen in niobium-based devices and shown how standard fabrication processes introduce these hydrides, developing strategies to mitigate their formation.1 Furthermore, we have characterized the metal-substrate interface, including the loss of niobium-silicides formed at that interface, and developed silicon surface treatments that reduce atomic scale roughness and oxygen content at the metal-substrate and Josephson junction interfaces.2-4 By developing the connection between materials properties and the overall performance of superconducting quantum circuitry, we can develop fabrication strategies to mitigate material losses, thus supporting the ongoing efforts to enhance coherence time in superconducting quantum devices. 1. Torres-Castanedo, C. G.*, Goronzy, D. P.*, et al., Adv. Funct. Mater., 2401365 (2024) 2. Lu, X., et al., Phys. Rev. Materials 6, 064402 (2022) 3. Berti, G., Appl. Phys. Lett. 122, 192605 (2023) 4. Kopas, C. J., Goronzy, D. P., et al., arXiv:2408.02863 (2024)

Goronzy, Dominic P.↗

DOE OSTI2024

Evaluation of Clamshell Current Coupler for Online Frequency Domain and Spread Spectrum Time Domain Reflectometry to Detect Anomalies in Energized Cables

This document describes adaptation and evaluation of a clamshell inductive current coupler for online reflectometry testing (both frequency domain reflectometry and spread spectrum time domain reflectometry) to evaluate cable insulation degradation and anomalies. Safety-critical nuclear power plant cables were initially qualified for 40 years. However, as plants extend their operating licenses to 60 and 80 years, justification for continued safe operation includes test and monitoring programs. These will become more important as the industry moves to condition based qualification programs. Cable test programs traditionally involve manual interventions to disconnect cables, perform one or several tests, then reconnect the systems, usually during refueling outages occurring only every 18 to 24 months. This poses an operational burden that can be minimized by online testing or periodic connection to a coupler that may remain on the cable of interest or be clamped onto the cable without de-termination. This work investigates the adaptation of a clamshell inductive current coupler for either frequency domain reflectometry or spread-spectrum time domain reflectometry. The reflectometry test instrument injects a broad-band chirp or pseudo-noise signal onto a cable conductor and monitors for a reflected signal indicative of an impedance change caused by a damage condition. The instrument maximum input signal levels are typically 10 to 30 volts or less and the instruments will be damaged if subjected to 60 Hz power line voltages of 110, 220, or 480 VAC. One commercial spread-spectrum time domain reflectometry system has circuitry suitable for voltages up to 1 kV, but typical reflectometry tests are performed on de-energized cables. The clamshell inductive coupler provides >60 dB of 60 Hz attenuation with less than 10 dB loss in the 1-500 MHz test bandwidth of interest. An energized cable was successfully tested up to 6.7 kVp-p and frequency response plots imply that the tests could be extended to 10 kV or higher energized levels.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Revolutionizing Neuromorphic Computing for Science (Brochure on the 2024 ASCR Workshop on Neuromorphic Computing for Science)

The ASCR basic research needs for Neuromorphic Computing for Science workshop was held in September 2024. The workshop brochure and report aim to inform and draft a set of grand challenges for advancing the field of neuromorphic computing and developing proof of principle neuromorphic circuits applicable for High Performance Computer (HPC) acceleration for scientific discovery, and brainstorm ideas needed for a successful, robust, and world leading basic research program. The resulting priority research directions are: (1) Neuromorphic computing circuit primitives; (2) Connectivity, communication, and hardware integration; (3) Neuroscience-derived dynamics and algorithms; and (4) Ecosystem for scalable neuromorphic co-design. Breakthroughs in understanding, designing, and prototyping the circuitry and simulation capabilities for a truly neuromorphic computer are essential to enable progress in the field.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Revolutionizing Neuromorphic Computing for Science (Report for the 2024 ASCR Workshop on Neuromorphic Computing for Science)

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗

DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗

DOE OSTI2024

Fabrication of a Point-Like Transmission Target for Reducing Computed Tomography Imaging Artifacts

In this study, we address the challenge of enhancing image quality and spatial resolution in computed tomography (CT) imaging by introducing simulation and fabrication of high aspect ratio, point-like transmission targets. Utilizing advanced electroplating techniques, traditionally employed in the fabrication of Through Substrate Via (TSV) interconnects for CMOS circuitry, we successfully embed copper targets within silicon substrates. This method allows us to create high-aspect-ratio features specifically designed for X-ray transmission targets, resulting in micro targets that exhibit a volume increase compared to conventional evaporated surface targets. Furthermore, we present simulation results of the X-ray spectrum generated by these targets, demonstrating their potential to significantly improve both image quality and spatial resolution in CT applications. Our findings suggest that leveraging advanced fabrication techniques can open new avenues for the development of enhanced imaging technologies in medical diagnostics and beyond.

47 OTHER INSTRUMENTATION↗

DOE OSTI2024

Integrated Spatial, Spectral, & Temporal Optical Reflectance System for Precision Occupancy & Location Sensing to Improve Building Energy Efficiency

Buildings consume approximately 35% of the electricity used in the U.S. and building owners can significantly reduce this energy use by providing services like heating, electrical power and lighting only when people are present. The ARPAe funded program titled “INTEGRATED SPATIAL, SPECTRAL, & TEMPORAL OPTICAL REFLECTANCE SYSTEM FOR PRECISION OCCUPANCY & LOCATION SENSING TO IMPROVE BUILDING ENERGY EFFICIENCY” demonstrates how a low cost sensor technology developed for measuring distances can be used to count and locate occupants with a high degree of precision with a very low error rates. This platform tells a building control system where occupants are located (but not who they are) so that energy consuming services can be provided only when the services are needed by building occupants. The original proof of concept involved using low cost, commercially available time-of-flight (TOF) sensors that measure distance, but the performance of these existing sensors was lacking, as they could not operate properly in the presence of sunlight, which blinded the simple TOF sensors and limited their utility in buildings. This project proposed a powerful new class of TOF sensors that used state-of-the-art integrated circuit (IC) fabrication processes that combined advanced photonics with conventional silicon chip circuitry for improved sensor performance. An equally important part of this project was to find ways to maximize occupant count and location accuracy while using the fewest number of sensors possible, in order to keep costs low. By using building blueprints to create digital twins of commercial building spaces, the team developed new algorithms to maximize occupant count and tracking accuracy by properly locating the minimum number of sensors at just the right spots in the building. This capability not only minimizes system costs but also simplified sensor installation and system commissioning. Our simulations of our sensor networks for a range of commercial floorplan designs demonstrated that our installed cost target of $0.08/sqft was attainable, though not fully demonstrated during the project. Finally, we noted that the TOF sensor concept could provide a valuable role in health and eldercare by tracking patients without the need for worn sensors and would be useful for fall detection and other patient safety metrics, including tracking healthcare/patient interactions. We feel that, when fully developed, this new class of sophisticated TOF sensors and support software will be a powerful new approach to improving building energy efficiency based on occupant centric control platforms and will also open new levels of patient safety in healthcare operations. To realize this potential, the team formed the Troy Sensor Company LLC to oversee licensing of the programs patents and continue to seek commercialization of this program’s activity sensing technologies.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2024

High Precision, High Frequency Printed Antennas

An emerging trend in advanced manufacturing is printed electronics and sensors. The ability to print customized electronics and sensors integrated into functional packages is a growing need within a variety of growing markets such as smart manufacturing, internet of things (IoT), and the small satellite industry. Both Oak Ridge National Laboratory (ORNL) and the MITRE Corporation have seedling research efforts evaluating the potential for future printed electronic systems. High frequency, wide-bandwidth phased array antennas (i.e. >45 GHz) open the door to new applications. However, such sensors require currently prohibitively small feature sizes for commercial 3D printing technologies along with increasing challenges with connecting the driving electronics to such features. An additional finding with related advanced manufacturing challenges is the rapid production of 3D additive connectors for integration with commercial printed circuit boards (PCBs), primarily for advanced in-circuit inspection techniques. This work is developing additive manufacturing processes for producing connected and conductive fine scale 3D features. The primary focus was on aerosol-jet printing (AJP), which has a small minimum resolution (<50 µm) but is traditionally printed flat with small height/width aspect ratios <<1, and developing controls to enable fully 3D, high aspect ratio, and unsupported features. In Phase 1 of this effort, baselines of process performance were characterized, and test coupons produced for both ultra-high frequency antennas and microstructures to support reverse engineering of PCBs. In Phase 2, these efforts will be extended for system demonstration of ultra-high frequency antenna arrays, as well as reverse engineering circuitry for dense PCBs.

42 ENGINEERING↗

DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗