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DOE OSTI2020

Noise resilience of variational quantum compiling

Variational hybrid quantum-classical algorithms (VHQCAs) are near-term algorithms that leverage classical optimization to minimize a cost function, which is efficiently evaluated on a quantum computer. Recently VHQCAs have been proposed for quantum compiling, where a target unitary U is compiled into a short-depth gate sequence V. In this work, we report on a surprising form of noise resilience for these algorithms. Namely, we find one often learns the correct gate sequence V (i.e. the correct variational parameters) despite various sources of incoherent noise acting during the cost-evaluation circuit. Our main results are rigorous theorems stating that the optimal variational parameters are unaffected by a broad class of noise models, such as measurement noise, gate noise, and Pauli channel noise. Furthermore, our numerical implementations on IBM's noisy simulator demonstrate resilience when compiling the quantum Fourier transform, Toffoli gate, and W-state preparation. Hence, variational quantum compiling, due to its robustness, could be practically useful for noisy intermediate-scale quantum devices. Finally, we speculate that this noise resilience may be a general phenomenon that applies to other VHQCAs such as the variational quantum eigensolver.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS1985

Generalized reciprocity theorem for semiconductor devices

A reciprocity theorem is presented that relates the short-circuit current of a device, induced by a carrier generation source, to the minority-carrier Fermi level in the dark. The basic relation is general under low injection. It holds for three-dimensional devices with position dependent parameters (energy gap, electron affinity, mobility, etc.), and for transient or steady-state conditions. This theorem allows calculation of the internal quantum efficiency of a solar cell by using the analysis of the device in the dark. Other applications could involve measurements of various device parameters, interfacial surface recombination velocity at a polcrystalline silicon emitter contact, for rexample, by using steady-state or transient photon or mass-particle radiation.

Misiakos, K.↗

NASA NTRS1985

Heavy doping effects in high efficiency silicon solar cells

The use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells was examined. The results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contact are presented. A reciprocity theorem is presented that relates the short circuit current of a device, induced by a carrier generation source, to the minority carrier Fermi level in the dark. A method for accurate measurement of minority-carrier diffusion coefficients in silicon is described.

Lindholm, F. A.↗

DOE OSTI2021

Universal Compiling and (No-)Free-Lunch Theorems for Continuous-Variable Quantum Learning

Quantum compiling, where a parameterized quantum circuit is trained to learn a target unitary, is an important primitive for quantum computing that can be used as a subroutine to obtain optimal circuits or as a tomographic tool to study the dynamics of an experimental system. While much attention has been paid to quantum compiling on discrete-variable hardware, less has been paid to compiling in the continuous-variable paradigm. Here we motivate several, closely related, short-depth continuous-variable algorithms for quantum compilation. We analyze the trainability of our proposed cost functions and numerically demonstrate our algorithms by learning arbitrary Gaussian operations and Kerr nonlinearities. We further make connections between this framework and quantum learning theory in the continuous-variable setting by deriving no-free-lunch theorems. These generalization bounds demonstrate a linear resource reduction for learning Gaussian unitaries using entangled coherent-Fock states and an exponential resource reduction for learning arbitrary unitaries using two-mode-squeezed states.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1988

Hardware proofs using EHDM and the RSRE verification methodology

Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system.

Butler, Ricky W.↗

DOE OSTI2022

Quantum Circuits for the Preparation of Spin Eigenfunctions on Quantum Computers

The application of quantum algorithms to the study of many-particle quantum systems requires the ability to prepare wave functions that are relevant in the behavior of the system under study. Hamiltonian symmetries are important instruments used to classify relevant many-particle wave functions and to improve the efficiency of numerical simulations. In this work, quantum circuits for the exact and approximate preparation of total spin eigenfunctions on quantum computers are presented. Two different strategies are discussed and compared: exact recursive construction of total spin eigenfunctions based on the addition theorem of angular momentum, and heuristic approximation of total spin eigenfunctions based on the variational optimization of a suitable cost function. The construction of these quantum circuits is illustrated in detail, and the preparation of total spin eigenfunctions is demonstrated on IBM quantum devices, focusing on three- and five-spin systems on graphs with triangle connectivity.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1974

An implicit sampling theorem for bounded bandlimited functions

A rigorous proof of the 'strong bias tone' scheme is embodied in the implicit sampling theorem. The representation of signals that are sample functions of possible nonstationary random processes being of principal interest, the proof could not directly invoke results from classical analysis, which depend on the existence of the Fourier transform of the function under consideration; rather, it is based on Zakai's (1965) theorem on the series expansion of functions, band-limited under a suitably extended definition. A practical circuit that restores an approximate version of the signal from its sine-wave-crossings is presented and possible improvements to it are discussed.

Bar-David, I.↗

DOE OSTI2023

Short-Depth QAOA circuits and Quantum Annealing on Higher-Order Ising Models (Rev.2)

The Quantum Alternating Operator Ansatz (QAOA) and Quantum Annealing (QA) are quantum algorithms that are both based on the adiabatic theorem and both have the goal of sampling the optimal solution(s) of combinatorial optimization problems. Quantum annealing has been physically instantiated on D-Wave devices using superconducting flux qubits, and QAOA can be programmed on digital gate-model quantum computers such as the programmable superconducting transmon qubits devices of the IBMQ series, for instance ibm washington. QAOA and QA address the same types of problems, but it is unclear how they will scale to large problem sizes and to larger and higher-fidelity quantum computers. In this article, we present a direct comparison between QAOA, one and two rounds, run on all 127 qubits of ibm washington and QA run on D-Wave Advantage system4.1 and Advantage system6.1. The problems which allow for this comparison are random Ising model problems whose connectivity matches the heavy hexagonal lattice topology of ibm washington and the Pegasus graph connectivity of the two D-Wave devices. We create two classes of problem instances for this comparison: one with higher order terms (ZZZ variable interactions), linear terms, and quadratic terms, and a separate problem type with only linear and quadratic terms. Our QAOA circuits are novel and extremely short depth, with a CNOT depth of 6 per round, which allows whole chip usage of ibm washington’s heavy hexagonal lattice and can be applied to future heavy-hex chips. We also test the effectiveness of the error suppression technique digital dynamical decoupling on the QAOA circuits. The QAOA circuits compiled to ibm washington are composed of several thousand circuit instructions, approximately 3, 000 depending on the details of the circuit, making these some the largest quantum circuits ever executed on a digital quantum processor. QAOA and QA are compared against the classical heuristic algorithm of simulated annealing and all problem instances are exactly solved using CPLEX in order to evaluate which samplers, if any, correctly found the ground state solution(s) of the problem instances. We find that (i) QA outperforms QAOA on all problem instances, (ii) QAOA samples the problems better than random sampling, and (iii) QAOA angle computation exhibits clear parameter concentration across the ensemble of Ising models.

127 Qubits↗

NASA NTRS1983

Hierarchical Design and Verification for VLSI

The specification and verification work is described in detail, and some of the problems and issues to be resolved in their application to Very Large Scale Integration VLSI systems are examined. The hierarchical design methodologies enable a system architect or design team to decompose a complex design into a formal hierarchy of levels of abstraction. The first step inprogram verification is tree formation. The next step after tree formation is the generation from the trees of the verification conditions themselves. The approach taken here is similar in spirit to the corresponding step in program verification but requires modeling of the semantics of circuit elements rather than program statements. The last step is that of proving the verification conditions using a mechanical theorem-prover.

Shostak, R. E.↗

DOE OSTI2026

Quantum Time-Space Tradeoffs for Matrix Problems

We consider the time and space required for quantum computers to solve a wide variety of problems involving matrices, many of which have only been analyzed classically in prior work. Our main results show that for a range of linear algebra problems—including matrix-vector product, matrix inversion, matrix multiplication and powering—existing classical time-space tradeoffs, several of which are tight for every space bound, also apply to quantum algorithms with at most a constant factor loss. For example, for almost all fixed matrices 𝐴, including the discrete Fourier transform matrix, we prove that quantum circuits with at most 𝑇 input queries and 𝑆 qubits of memory require 𝑇 = Ω⁢(𝑛 2 /𝑆) to compute matrix-vector product 𝐴⁢𝑥 for 𝑥 ∈{0,1 𝑛 . We similarly prove that matrix multiplication for 𝑛 ×𝑛 binary matrices requires 𝑇 = Ω⁢(𝑛 3 /$\sqrt{𝑆}$). Because many of our lower bounds are matched by deterministic algorithms with the same time and space complexity, our results show that quantum computers cannot provide any asymptotic advantage for these problems with any space bound. We obtain matching lower bounds for the stronger notion of quantum cumulative memory complexity—the sum of the space per layer of a circuit. We also consider Boolean (i.e., AND-OR) matrix multiplication and matrix-vector products, improving the previous quantum time-space tradeoff lower bounds for 𝑛 × 𝑛 Boolean matrix multiplication to 𝑇 = Ω⁢(𝑛 2.5 /𝑆 1/4 ) from 𝑇 = Ω⁢(𝑛 2.5 /𝑆 1/2 ). Our improved lower bound for Boolean matrix multiplication is based on a new coloring argument that extracts more from the strong direct product theorem that was the basis for prior work. To obtain our tight lower bounds for linear algebra problems, we require much stronger bounds than strong direct product theorems. We obtain these bounds by adding a new bucketing method to the quantum recording-query technique of Zhandry that lets us apply classical arguments to upper bound the success probability of quantum circuits.

lower bounds↗

NASA NTRS1991

Formal hardware verification of digital circuits

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

Joyce, J.↗

NASA NTRS1994

Formal semantics for a subset of VHDL and its use in analysis of the FTPP scoreboard circuit

In the first part of the report, we give a detailed description of an operational semantics for a large subset of VHDL, the VHSIC Hardware Description Language. The semantics is written in the functional language Caliban, similar to Haskell, used by the theorem prover Clio. We also describe a translator from VHDL into Caliban semantics and give some examples of its use. In the second part of the report, we describe our experience in using the VHDL semantics to try to verify a large VHDL design. We were not able to complete the verification due to certain complexities of VHDL which we discuss. We propose a VHDL verification method that addresses the problems we encountered but which builds on the operational semantics described in the first part of the report.

Bickford, Mark↗

NASA NTRS1991

Transfer Functions Via Laplace- And Fourier-Borel Transforms

Approach to solution of nonlinear ordinary differential equations involves transfer functions based on recently-introduced Laplace-Borel and Fourier-Borel transforms. Main theorem gives transform of response of nonlinear system as Cauchy product of transfer function and transform of input function of system, together with memory effects. Used to determine responses of electrical circuits containing variable inductances or resistances. Also possibility of doing all noncommutative algebra on computers in such symbolic programming languages as Macsyma, Reduce, PL1, or Lisp. Process of solution organized and possibly simplified by algebraic manipulations reducing integrals in solutions to known or tabulated forms.

Can, Sumer↗

DOE OSTI2024

Demonstration of the rodeo algorithm on a quantum computer

The rodeo algorithm is an efficient algorithm for eigenstate preparation and eigenvalue estimation for any observable on a quantum computer. This makes it a promising tool for studying the spectrum and structure of atomic nuclei as well as other fields of quantum many-body physics. The only requirement is that the initial state has sufficient overlap probability with the desired eigenstate. While it is exponentially faster than well-known algorithms such as phase estimation and adiabatic evolution for eigenstate preparation, it has yet to be implemented on an actual quantum device. In this work, we apply the rodeo algorithm to determine the energy levels of a random one-qubit Hamiltonian, resulting in a relative error of 0.08% using mid-circuit measurements on the IBM Q device Casablanca. This surpasses the accuracy of directly-prepared eigenvector expectation values using the same quantum device. We take advantage of the high-accuracy energy determination and use the Hellmann-Feynman theorem to compute eigenvector expectation values for a different random one-qubit observable. For the Hellmann-Feynman calculations, we find a relative error of 0.7%. Here, we conclude by discussing possible future applications of the rodeo algorithm for multi-qubit Hamiltonians.

algorithm↗

NASA NTRS1997

Analysis of Stub Loaded Microstrip Patch Antennas

A microstrip patch antenna fed by a coaxial probe and reactively loaded by a open circuited microstrip line has been used previously to produce circular polarization and also as a building block for a series fed microstrip patch array. Rectangular and circular patch antennas loaded with a microstrip stub were previously analyzed using the generalized Thevenin theorem. In the Thevenin theorem approach, the mutual coupling between the patch current and the surface current on the stub was not taken into account. Also, the Thevenin theorem approach neglects continuity of current at the patch-stub junction. The approach in this present paper includes the coupling between the patch and stub currents as well as continuity at the patch-stub junction. The input impedance for a stub loaded microstrip patch is calculated by the general planar dielectric dyadic Green's function approach in the spectral domain, as was initiated much earlier and has been extensively expanded upon and utilized successfully throughout the literature for microstrip antenna configurations. Using the spectral domain dyadic Green s function derived earlier with the electric field integral equation (EFIE), the problem is formulated by using entire domain basis functions to represent the surface current densities on the patch, the loading stub and the attachment mode at the junction. Galerkin's procedure is used to reduce the EFIE to a matrix equation, which is then solved to obtain the amplitudes of the surface currents. These surface currents are then used for calculating the input impedance of stub loaded rectangular and circular microstrip patches. Numerical results are compared with measured results and with previous results calculated by the Thevenin's theorem approach.

Deshpande, M. D.↗

NASA NTRS1997

Analysis of Stub Loaded Microstrip Patch Antennas

A microstrip patch antenna fed by a coaxial probe and reactively loaded by a open circuited microstrip line has been used previously to produce circular polarization[ l] and also as a building block for a series fed microstrip patch array [2]. Rectangular and circular patch antennas loaded with a microstrip stub were previously analyzed using the generalized Thevenin theorem [2,3]. In the Thevenin theorem approach, the mutual coupling between the patch current and the surface current on the stub was not taken into account. Also, the Thevenin theorem approach neglects continuity of current at the patch-stub junction. The approach in this present paper includes the coupling between the patch and stub currents as well as continuity at the patch-stub junction.

Bailey, M. C.↗

NASA NTRS1995

DRS: Derivational Reasoning System

The high reliability requirements for airborne systems requires fault-tolerant architectures to address failures in the presence of physical faults, and the elimination of design flaws during the specification and validation phase of the design cycle. Although much progress has been made in developing methods to address physical faults, design flaws remain a serious problem. Formal methods provides a mathematical basis for removing design flaws from digital systems. DRS (Derivational Reasoning System) is a formal design tool based on advanced research in mathematical modeling and formal synthesis. The system implements a basic design algebra for synthesizing digital circuit descriptions from high level functional specifications. DRS incorporates an executable specification language, a set of correctness preserving transformations, verification interface, and a logic synthesis interface, making it a powerful tool for realizing hardware from abstract specifications. DRS integrates recent advances in transformational reasoning, automated theorem proving and high-level CAD synthesis systems in order to provide enhanced reliability in designs with reduced time and cost.

Bose, Bhaskar↗

NASA NTRS1990

Machine-checked proofs of the design and implementation of a fault-tolerant circuit

A formally verified implementation of the 'oral messages' algorithm of Pease, Shostak, and Lamport is described. An abstract implementation of the algorithm is verified to achieve interactive consistency in the presence of faults. This abstract characterization is then mapped down to a hardware level implementation which inherits the fault-tolerant characteristics of the abstract version. All steps in the proof were checked with the Boyer-Moore theorem prover. A significant results is the demonstration of a fault-tolerant device that is formally specified and whose implementation is proved correct with respect to this specification. A significant simplifying assumption is that the redundant processors behave synchronously. A mechanically checked proof that the oral messages algorithm is 'optimal' in the sense that no algorithm which achieves agreement via similar message passing can tolerate a larger proportion of faulty processor is also described.

Bevier, William R.↗