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A custom designed SRAM was used to measure the thickness of integrated circuit over layers and the epi-layer thickness using alpha particles and a test SRAM. The over layer consists of oxide, nitride, metal, and junction regions.
Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).
A method was developed for measuring nondestructively the depth of planar p-n junctions in simple devices as well as in integrated-circuit structures with the electron-beam induced current (EBIC) by scanning parallel to the junction in a scanning electron microscope (SEM). The results were found to be in good agreement with those obtained by the commonly used destructive method of lapping at an angle to the junction and staining to reveal the junction.
Contents include following: film deposition technique; laser ablation; magnetron sputtering; sequential evaporation; microwave substrates; film characterization at microwave frequencies; complex conductivity; magnetic penetration depth; surface impedance; planar single-mode filters; small antennas; antenna arrays phase noise; tunable oscillations; hybrid superconductor/semiconductor receiver front ends; and noise modeling.
A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.
A thermal cycling experiment was performed on GaAs solar cells to establish the electrical and structural integrity of these cells under the temperature conditions of a simulated low-Earth orbit of 3-year duration. Thirty single junction GaAs cells were obtained and tests were performed to establish the beginning-of-life characteristics of these cells. The tests consisted of cell I-V power output curves, from which were obtained short-circuit current, open circuit voltage, fill factor, and cell efficiency, and optical micrographs, spectral response, and ion microprobe mass analysis (IMMA) depth profiles on both the front surfaces and the front metallic contacts of the cells. Following 5,000 thermal cycles, the performance of the cells was reexamined in addition to any factors which might contribute to performance degradation. It is established that, after 5,000 thermal cycles, the cells retain their power output with no loss of structural integrity or change in physical appearance.
Recent advances in solar cell technology have led to the development of laboratory cells with efficiencies above 15% and production cells with efficiencies in the area of 13%. The increased output is largely the result of increases in the short-circuit current. The most significant gain in the amount of light entering the cell has been obtained through surface texturing by chemical etching techniques. Sheet resistances resulting from phosphorus diffusion in the 800 C temperature range yield junction depths on the order of 0.1 micrometer, leading to significant increases in the blue region of the cell spectral response. The inclusion of a back surface field in 10 ohm-cm cells has produced an increase in open-circuit voltage of about 50 mV and an increase in the minority carrier lifetime. It appears that a low emitter efficiency of the diffused region is the cause of poor voltages. Future research will be primarily directed toward correcting this deficiency and toward the development of low cost production methods.
The Surface Science Laboratories at the University of Alabama in Huntsville (UAH) are equipped with x-ray photoelectron spectroscopy (XPS or ESCA) and Auger electron spectroscopy (AES) facilities. These techniques provide information from the uppermost atomic layers of a sample, and are thus truly surface sensitive. XPS provides both elemental and chemical state information without restriction on the type of material that can be analyzed. The sample is placed into an ultra high vacuum (UHV) chamber and irradiated with x-rays which cause the ejection of photoelectrons from the sample surface. Since x-rays do not normally cause charging problems or beam damage, XPS is applicable to a wide range of samples including metals, polymers, catalysts, and fibers. AES uses a beam of high energy electrons as a surface probe. Following electronic rearrangements within excited atoms by this probe, Auger electrons characteristic of each element present are emitted from the sample. The main advantage of electron induced AES is that the electron beam can be focused down to a small diameter and localized analysis can be carried out. On the rastering of this beam synchronously with a video display using established scanning electron microscopy techniques, physical images and chemical distribution maps of the surface can be produced. Thus very small features, such as electronic circuit elements or corrosion pits in metals, can be investigated. Facilities are available on both XPS and AES instruments for depth-profiling of materials, using a beam of argon ions to sputter away consecutive layers of material to reveal sub-surface (and even semi-bulk) analyses.
This communication considers the design of the front grid contact of np GaAs solar cells for high efficiency concentrator applications. This design involves shadowing, contact resistance, and active layer sheet resistance losses, and at high concentrations, the power loss due to voltage drop on the resistance of the grid fingers should be considered. Analysis of the performance can be calculated as a function of junction depth and surface recombination velocity. The junction depth can be optimized by considering its effect on the collection efficiency of the dark current-voltage characteristics or the open circuit voltage, and on the series resistance loss or the fill factor for material parameters. The choice of the material parameters, calculation of the short circuit current, the selection of the n layer thickness, and the cell maximum power and efficiency are discussed. It is concluded that optimized multi-grid structures should allow the use of 10 by 10 sq cm cells with good efficiencies at high concentration ratios, and efficiencies of 22 to 25% should be obtainable from large area cells at concentrations of 40 AM1.
A continuous p-type GaAs epilayer has been deposited on an n-type sawtooth GaAs surface using MOCVD. A wet chemical etching process was used to expose the intersecting (111)Ga and (-1 -1 1)Ga planes with 6-micron periodicity. Charge-collection microscopy was used to verify the presence of the pn junction thus formed and to measure its depth. The ultimate goal of this work is to fabricate a V-groove GaAs cell with improved absorptivity, high short-circuit current, and tolerance to particle radiation.
Microwave transmission measurements through YBa2Cu3O(7-delta) (YBCO) high-transition-temperature superconducting thin films on lanthanum aluminate (LaAlO3) have been performed in a coaxial line at 10 GHz. LaAlO3 substrates were ultrasonically machined into washer-shaped discs, polished, and coated with laser-ablated YBCO. These samples were mounted in a 50-ohm coaxial air line to form a short circuit. The power transmitted through the films as a function of temperature was used to calculate the normal state conductivity and the magnetic penetration depth for the films.
A method of preparation of specimens of non-electropolishable materials for analysis by atom probes is being developed as a superior alternative to a prior method. In comparison with the prior method, the present method involves less processing time. Also, whereas the prior method yields irregularly shaped and sized specimens, the present developmental method offers the potential to prepare specimens of regular shape and size. The prior method is called the method of sharp shards because it involves crushing the material of interest and selecting microscopic sharp shards of the material for use as specimens. Each selected shard is oriented with its sharp tip facing away from the tip of a stainless-steel pin and is glued to the tip of the pin by use of silver epoxy. Then the shard is milled by use of a focused ion beam (FIB) to make the shard very thin (relative to its length) and to make its tip sharp enough for atom-probe analysis. The method of sharp shards is extremely time-consuming because the selection of shards must be performed with the help of a microscope, the shards must be positioned on the pins by use of micromanipulators, and the irregularity of size and shape necessitates many hours of FIB milling to sharpen each shard. In the present method, a flat slab of the material of interest (e.g., a polished sample of rock or a coated semiconductor wafer) is mounted in the sample holder of a dicing saw of the type conventionally used to cut individual integrated circuits out of the wafers on which they are fabricated in batches. A saw blade appropriate to the material of interest is selected. The depth of cut and the distance between successive parallel cuts is made such that what is left after the cuts is a series of thin, parallel ridges on a solid base. Then the workpiece is rotated 90 and the pattern of cuts is repeated, leaving behind a square array of square posts on the solid base. The posts can be made regular, long, and thin, as required for samples for atom-probe analysis. Because of their small volume and regularity, the amount of FIB-milling time can be much less than that of the method of sharp shards. Individual posts can be broken off for mounting in a manner similar to that of the method of sharp shards. Alternatively, the posts can be left intact on the base and the base can be cut to a small square (e.g., 3 by 3 mm) suitable for mounting in an atom probe of a type capable of accepting multiple-tip specimens. The advantage of multiple-tip specimens is the possibility of analyzing many tips without the time-consuming interchange of specimens.
An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.
The features, strong points and shortcomings of 10 numerical models commonly applied to assessing photovoltaic performance are discussed. The models range in capabilities from first-order approximations to full circuit level descriptions. Account is taken, at times, of the cell and module characteristics, the orientation and geometry, array-level factors, the power-conditioning equipment, the overall plant performance, O and M effects, and site-specific factors. Areas of improvement and/or necessary extensions are identified for several of the models. Although the simplicity of a model was found not necessarily to affect the accuracy of the data generated, the use of any one model was dependent on the application.
This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.
A system has been developed for detecting the level of a liquid in a tank wherein a capacitor positioned in the tank has spaced plates which are positioned such that the dielectric between the plates will be either air or the liquid, depending on the depth of the liquid in the tank. An oscillator supplies a sine wave current to the capacitor and a coaxial cable connects the capacitor to a measuring circuit outside the tank. If the cable is very long or the capacitance to be measured is low, the capacitance inherent in the coaxial cable will prevent an accurate reading. To avoid this problem, an inductor is connected across the cable to form with the capacitance of the cable a parallel resonant circuit. The impedance of the parallel resonant circuit is infinite, so that attenuation of the measurement signal by the stray cable capacitance is avoided.
This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.