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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1978

Designing low cost receivers for general aviation users

Approaches to the design of a low cost receiver which meets all IFR requirements for 2D area navigation are discussed. These include: (1) using current technology with a minimum of specialized LSI, a minimum of circuit complexity, and minimal use of critical components; (2) emphasized microprocessor technology; and (3) a special analog/digital chip fabrication. A low cost GPS receiver configuration with a single sequencing tracking channel is examined. Problem areas are indicated.

Natali, F. D.↗
NASA NTRS1980

GPS/REFSAT definition study report for low-cost terminals

A relay transponder, located either on a satellite in geostationary orbit or on a local tower to relay acquisition-aiding data, ephemerides, etc, from a ground-based remote control station to a GPS civil user terminal located on a ship or land-transportation vehicle is described. Termed REFSAT (Reference Satellite), this concept reduces the circuit complexity and cost of user terminals. The various systems needed to implement the REFSAT concept for low-cost, GPS civil terminals are defined. The GPS/REFSAT system compatible with the NAVSTAR GPS system consists of a geostationary relay satellite, civil user terminals, and the central facility which performs operations common to all users for relay via the space segment. A GPS/REFSAT system utilizing a local tower for the relay transponder is described, results of a study of civil user requirements are presented, and specifications for the GPS/REFSAT system and its individual segments are included.

Source record↗
NASA NTRS1991

Application of convolve-multiply-convolve SAW processor for satellite communications

There is a need for a satellite communications receiver than can perform simultaneous multi-channel processing of single channel per carrier (SCPC) signals originating from various small (mobile or fixed) earth stations. The number of ground users can be as many as 1000. Conventional techniques of simultaneously processing these signals is by employing as many RF-bandpass filters as the number of channels. Consequently, such an approach would result in a bulky receiver, which becomes impractical for satellite applications. A unique approach utilizing a realtime surface acoustic wave (SAW) chirp transform processor is presented. The application of a Convolve-Multiply-Convolve (CMC) chirp transform processor is described. The CMC processor transforms each input channel into a unique timeslot, while preserving its modulation content (in this case QPSK). Subsequently, each channel is individually demodulated without the need of input channel filters. Circuit complexity is significantly reduced, because the output frequency of the CMC processor is common for all input channel frequencies. The results of theoretical analysis and experimental results are in good agreement.

Lie, Y. S.↗
NASA NTRS1986

Practical design of magnetic heading sensors

Although fluxgate magnetometers have been in use for many years, and a number of theoretical studies of these sensors are available, very little information has been published on the engineering choices relating to the detailed design of magnetometers intended for navigational applications in aircraft and other vehicles. This paper addresses some of the problems encountered in the design of the sensing head, the choice of operating mode, and the design of the supporting electronics for a simple low-cost magnetometer system which will produce a digital readout of the magnetic heading of the vehicle in which it is mounted. A major goal of this study has been to develop a design which minimizes circuit complexity, is easy to fabricate and calibrate, and utilizes a minimum of specialized components. Such a magnetometer system is intended either as a stand-alone indicating instrument or as a source of magnetic heading information for a more sophisticated navigational system.

Garner, H. D.↗
NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗
NASA NTRS2004

Design Space Issues for Intrinsic Evolvable Hardware

This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

Hereford, James↗
NASA NTRS2000

Displacement Damage in Bipolar Linear Integrated Circuits

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.↗
NASA NTRS1983

Probe Array for Testing Printed-Circuit Substrates

Array of tiny probes tests complex printed circuit boards prior to mounting of microcircuit chips and other active and passive components. Insertion and alignment of board, performance of entire computer-controlled test, and printing of results requires about a minute; performed manually same tests require as much as 30 hours.

Roison, A.↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS2024

Two mechanisms for the spontaneous emergence, execution, and reprogramming of chemical logic circuits

A key question in origin-of-life research is how primitive life or life-like systems obtained reusable and reprogrammable machinery of processing information to respond to various environmental and internal stimuli. One strategy to approach this question is to view living systems as universal chemical computers. This approach focuses upon uncovering how reusable and reprogrammable chemical NOT, AND, and OR logic gates could appear under prebiotically possible scenarios where simple chemicals and second- or lower-order reactions are more frequent than macromolecules and higher-order reactions. In this article, we theoretically model two generic mechanisms of forming Boolean gates based on geochemically plausible reaction systems that could have preceded complex biopolymers. The mechanisms exploit simple bistable autocatalytic systems to encode binary variables and use heterogeneous dilution rates to differentially activate or deactivate autocatalysis in different reactors. We found that NOT, AND, and OR gates, as well as more complex logic circuits, can spontaneously arise from connected, well-mixed flow reactors based on (i) catalysis by a heterodimer between mutually inhibitory autocatalysts or (ii) selectively permeable tunnels connecting reactors. Our results suggest that simple machinery can support the prebiotic emergence of complex chemical logic circuits and provide new guides for experimentally actualizing chemical computation.

Zhen Peng↗
NASA NTRS1985

Rotary Power Transformer and Inverter Circuit

Noise lower than with sliprings. Rotary transformer transfers electric power across rotary joint. No wearing contacts, no contact noise, and no contamination from lubricants or wear debris. Because additional inductor not required, size and complexity of circuit reduced considerably.

Mclyman, C. W. T.↗
NASA NTRS1988

Aerodynamic flow quality and acoustic characteristics of the 40- by 80-foot test section circuit of the National Full-Scale Aerodynamic Complex

The 40- by 80-foot wind tunnel circuit of the National Full-Scale Aerodynamic Complex (NFAC) has recently undergone major modifications and subsequently completed final acceptance testing. The initial testing and calibration of the wind tunnel are described and in many cases these results are compared with predictions derived from model tests and theoretical analyses. The wind tunnel meets or exceeds essentially all performance objectives. The facility runs smoothly and routinely at its maximum test-section velocity of 300 knots (Mach number = 0.45). An effective cooling air exchange system enables the wind tunnel to operate indefinitely at this maximum power condition. Throughout the operating envelope of the wind tunnel the test-section dynamic pressure is uniform to within + or - 0.5 deg, and the axial component of turbulence is generally less than 0.5 percent. Acoustic measurements indicate that, due to the low noise fans and acoustic treatment in the wind-tunnel circuit and test section, the background noise level in the test section is comparable to other large-scale acoustic wind tunnels in the United States and abroad.

Olson, Lawrence E.↗
NASA NTRS2011

Component-Level Electronic-Assembly Repair (CLEAR) Spacecraft Circuit Diagnostics by Analog and Complex Signature Analysis

The Component-Level Electronic-Assembly Repair (CLEAR) project at the NASA Glenn Research Center is aimed at developing technologies that will enable space-flight crews to perform in situ component-level repair of electronics on Moon and Mars outposts, where there is no existing infrastructure for logistics spares. These technologies must provide effective repair capabilities yet meet the payload and operational constraints of space facilities. Effective repair depends on a diagnostic capability that is versatile but easy to use by crew members that have limited training in electronics. CLEAR studied two techniques that involve extensive precharacterization of "known good" circuits to produce graphical signatures that provide an easy-to-use comparison method to quickly identify faulty components. Analog Signature Analysis (ASA) allows relatively rapid diagnostics of complex electronics by technicians with limited experience. Because of frequency limits and the growing dependence on broadband technologies, ASA must be augmented with other capabilities. To meet this challenge while preserving ease of use, CLEAR proposed an alternative called Complex Signature Analysis (CSA). Tests of ASA and CSA were used to compare capabilities and to determine if the techniques provided an overlapping or complementary capability. The results showed that the methods are complementary.

Oeftering, Richard C.↗
NASA NTRS1984

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Long, S. I.↗
NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗
NASA NTRS2007

Development of a Tunable Electromechanical Acoustic Liner for Engine Nacelles

This report describes the development of a tunable electromechanical Helmholtz resonator (EMHR) for engine nacelles using smart materials technology. This effort addresses both near-term and long-term goals for tunable electromechanical acoustic liner technology for the Quiet Aircraft Technology (QAT) Program. Analytical models, i.e. lumped element model (LEM) and transfer matrix (TM) representation of the EMHR, have been developed to predict the acoustic behavior of the EMHR. The models have been implemented in a MATLAB program and used to compare with measurement results. Moreover, the prediction performance of models is further improved with the aid of parameter extraction of the piezoelectric backplate. The EMHR has been experimentally investigated using standard two-microphone method (TMM). The measurement results validated both the LEM and TM models of the EMHR. Good agreement between predicted and measured impedance is obtained. Short- and open circuit loads define the limits of the tuning range using resistive and capacitive loads. There is approximately a 9% tuning limit under these conditions for the non-optimized resonator configuration studied. Inductive shunt loads result in a 3 degree-of-freedom DOF) system and an enhanced tuning range of over 20% that is not restricted by the short- and open-circuit limits. Damping coefficient ' measurements for piezoelectric backplates in a vacuum chamber are also performed and indicate that the damping is dominated by the structural damping losses, such as compliant boundaries, and other intrinsic loss mechanisms. Based on models of the EMHR, a Pareto optimization design of the EMHR has been performed for the EMHR with non-inductive loads. The EMHR with non-inductive loads is a 2DOF system with two resonant fiequencies. The tuning ranges of the two resonant frequencies of the EMHR with non-inductive loads cannot be optimized simultaneously; a trade-off (i.e., a Pareto solution) must be reached. The Pareto solution provides the information for a designer that shows how design trade-offs can be used to satisfy specific design requirements. The optimization design of the EMHR with inductive loads aims at optimal tuning of these three resonant fiequencies. The results indicate that it is possible to keep the acoustic reactance of the resonator close to a constant over a given frequency range. An effort to mimic the second layer of the NASA 2DOF liner using a piezoelectric composite diaphragm has been made. The optimal acoustic reactance of the second layer of the NASA 2DOF liner is achieved using a thin PVDF composite diaphragm, but matching the acoustic resistance requires further investigation. Acoustic energy harvesting is achieved by connecting the EMHR to an energy reclamation circuit that converts the ac voltage signal across the piezoceramic to a conditioned dc signal. Energy harvesting experiment yields 16 m W continuous power for an incident SPL of 153 dB. Such a level is sufficient to power a variety of low power electronic devices. Finally, technology transfer has been achieved by converting the original NASA ZKTL FORTRAN code to a MATLAB code while incorporating the models of the EMHR. Initial studies indicate that the EMHR is a promising technology that may enable lowpower, light weight, tunable engine nacelle liners. This technology, however, is very immature, and additional developments are required. Recommendations for future work include testing of sample EMHR liner designs in NASA Langley s normal incidence dual-waveguide and the grazing-incidence flow facility to evaluating both the impedance characteristics as well as the energy reclamation abilities. Additional design work is required for more complex tuning circuits with greater performance. Poor electromechanical coupling limited the electromechanical tuning capabilities of the proof of concept EMHR. Different materials than those studies and perhaps novel composite material systems may dramatically improvehe electromechanical coupling. Such improvements are essential to improved mimicking of existing double layer liners.

Liu, Fei↗