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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Y-Type Non-Fullerene Acceptors with Outer Branched Side Chains and Inner Cyclohexane Side Chains for 19.36% Efficiency Polymer Solar Cells

Raising the lowest unoccupied molecular orbital (LUMO) energy level of Y-type non-fullerene acceptors can increase the open-circuit voltage (V oc ) and thus the photovoltaic performance of the current top performing polymer solar cells (PSCs). One of the viable routes is demonstrated by the successful Y6 derivative of L8-BO with the branched alkyl chains at the outer side. This will introduce steric hindrance and reduce intermolecular aggregation, thus open up the bandgap and raise the LUMO energy level. To take further advantages of the steric hindrance influence on optoelectronic properties of Y6 derivatives, two Y-type non-fullerene acceptors of BTP-Cy-4F and BTP-Cy-4Cl are designed and synthesized by adopting outer branched side chains and inner cyclohexane side chains. An outstanding V oc of 0.937 V is achieved in the D18:BTP-Cy-4F binary blend devices along with a power conversion efficiency (PCE) of 18.52%. With the addition of BTP-eC9 to extend the absorption spectral coverage, a remarkable PCE of 19.36% is realized finally in the related ternary blend devices, which is one of the highest values for single-junction PSCs at present. The results illustrate the great potential of cyclohexane side chains in constructing high-performance non-fullerene acceptors and their PSCs.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Cost-Efficiency balanced polymer acceptors based on lowly fused Dithienopyrrolo[3, 2b]benzothiadiazole for 16.04% efficiency All-Polymer solar cells

All-polymer solar cells (All-PSCs) attracted increasing attention due to the outstanding thermal stability and mechanical properties. The current prevailing polymer acceptors for most efficient All-PSCs are polymerized high-performance small molecule acceptor of Y6, i.e. the dithienothiopheno[3,2-b]-pyrrolobenzothiadiazole (BTTP) based polymers. However, the BTTP-based polymers often show relatively shallow highest occupied molecular orbital (HOMO) energy level and high figure of merit (FOM), which limit the rational selection of paring donor polymers. Herein, we presented two low-cost polymer acceptors, namely as BTP-T2F and BTP-2T2F, based on lowly fused dithienopyrrolo[3,2b]benzothiadiazole (BTP, removing two thiophene cycles from BTTP). Here the BTP-based polymers exhibited deeper HOMO levels around –5.90 eV, which could match variable donor polymers with low-lying HOMO levels, such as low-cost PTQ10. Additionally, the synthesis was significantly simplified compared to BTTP-based polymers. A power conversion efficiency (PCE) of 14.32% was achieved in binary blend device containing PTQ10:BTP-2T2F. By adding a miscibility-enhancing PBDTCl-TPD as a third component, the top PCE of 16.04% was obtained in ternary blend All-PSCs. Combining the high device performance and low estimated cost, extraordinary cost-efficiency balance was realized within these BTP-based polymer acceptors.

36 MATERIALS SCIENCE↗
NASA NTRS1965

Delayed ripple counter simplifies square-root computation

Ripple subtract technique simplifies the logic circuitry required in a binary computing device to derive the square root of a number. Successively higher numbers are subtracted from a register containing the number out of which the square root is to be extracted. The last number subtracted will be the closest integer to the square root of the number.

Cliff, R.↗
NASA NTRS1966

Uniform codes.

Existence of q-ary uniform convolutional codes where q is any prime-power, noting error- correcting ability comparable to familiar maximal- length block codes

ENCODING↗
NASA NTRS1990

Quantized-"Gray-Scale" Electronic Synapses

Proposed array of programmable synaptic connections for electronic neural network applications offers multiple quantized levels of connection strength using only simple, two-terminal, binary microswitch devices. Subgrids in fine grid of programmable resistive connections connected externally in parallel to form coarser synaptic grid. By selection of pattern of connections in each subgrid, connection strength of synaptic node represented by that subgrid set at quantized "gray level". Device structures promise implementations of quantized-"gray-scale" synaptic arrays with very high density.

Lamb, James L.↗
NASA NTRS2011

Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications

A technique was developed to provide a reconfigurable high-precision micro - wave electrical phase delay for resonators and phase shifters. The invention employs multiple branches of transmission lines with open-ended or ground-ended terminations as configurable bits or digits. This technique minimizes the errors due to limited precision of switching devices. In addition, the proposed linear analytical approach significantly produces a much simpler design than that of other prior inventions at the time of this reporting. Microwave components such as filters, phase delay elements, or resonators require a method that can accurately adjust their frequency responses. Most tuning techniques offer very wide frequency tuning range; however, it is often difficult and expensive to tune their response in a very narrow operating frequency, especially when the tuning element reaches its minimum discrete step due to fabrication tolerances. The problem becomes worse as the operating frequency is in mm-wave frequency range (>26 GHz). The electrical tuning sensitivity of a microwave line is dependent on the position of the tuning element with respect to the reference termination. By placing this tuning element away from this reference with the main transmission line connecting the two elements together the sensitivity of the tuning element can change significantly. This concept can be used in the system that requires multiple tuning sensitivities. In this case, multiple tuning branches are superimposed in the main transmission line. The proposed invention allows the transmission-line electrical length to be accurately programmed using switching elements that have limited accuracy. The invention consists of multiple branches of transmission lines connected to discrete switching devices with open-ended terminations. They are used as discrete tuning elements. These elements are connected to the main microwave transmission line and are separated by a well-defined electrical degree spacing. Each branch is programmed to have different electrical degree sensitivity, such as a combination of discrete steps in each branch, which results in a reflective line with a unique effective phase response. To reduce the number of switching devices, it is desirable to program the devices in binary configuration where each branch represents one bit in the base-2 number system. This invention allows the transmission line electrical length to be tuned precisely with customizable sensitivity based on the known sensitivity of the base tuning circuit. The tuning resolution is dependent on the distance among tuning branches.

Hsieh, Wen-Ting↗
DOE OSTI2024

Investigation of an Intermittent Binary Control Strategy for Distributed Aerodynamic Control Devices for Load Alleviation in Wind Turbine Blades

A study was conducted of an intermittent binary control strategy for trailing edge flaps and leading edge spoilers installed on wind turbine blades for the purpose of load alleviation. Cost estimation models were developed for the systems to predict overall impact on levelized cost of energy over the lifecycle of the turbine system. Aeroelastic simulations of turbines with the control strategy implemented showed improved levelized cost for some, but not all cases.

17 WIND ENERGY↗
DOE OSTI2023

Asymmetric Electrode Work Function Customization via Top Electrode Replacement in Ferroelectric and Field–Induced Ferroelectric Hafnium Zirconium Oxide Thin Films

Non-volatile memory device structures such as ferroelectric random-access memory and ferroelectric tunnel junctions employ switchable spontaneous polarization to hold binary states. These devices can potentially benefit from the imposition of spontaneous internal biases and their resulting effect on the polarization properties of the ferroelectric (or field-induced ferroelectric/ antiferroelectric) layer. While HfO 2 -based thin films are ideal candidates for implementation into these devices due to their scalability and silicon compatibility, the phase purity of these oxides is sensitive to the selection of electrode material, preventing incorporation of asymmetric electrode layers into such structures. Within this work, electrode replacement following post-metallization anneal processing is introduced as a route to achieve ferroelectric and field-induced ferroelectric Hf x Zr 1–x O 2 (HZO) thin films with electrode-independent phase constitutions. The effects of this process and the corresponding internal biases imposed across the HZO layers due to asymmetric work functions are investigated. It is shown that internal biases vary in magnitude in accordance with prediction based on the work functions of the replaced electrode layers and affect remanent polarization magnitudes. Accordingly, electrode replacement presents a processing route that can readily produce HZO films with spontaneous internal biases and electrode- independent phase constitutions, facilitating implementation of these ferroelectrics into the next generation device structures.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Advancing subsurface analysis: Integrating computer vision and deep learning for the near real-time interpretation of borehole image logs in the Illinois Basin-Decatur Project

The accurate quantification and mapping of subsurface natural fracture systems using borehole imaging logs are critical for the success of CO 2 sequestration in geologic formations, optimization of engineered geothermal systems, and hydrocarbon production enhancement. However, traditional interpretation processes suffer from time-consuming procedures and human bias. To address these challenges and expedite fracture analysis, we investigated the application of integrated computer vision and DL workflows to automate image log analysis. Specifically, the design of our workflow was crafted to swiftly detect fractures and baffles by using actual electrical resistivity of borehole wall from microresistivity imaging device alongside their binary representation. This novel approach significantly reduces computational time while providing invaluable insights. By incorporating conventional logging and microseismic data, we present a regional subsurface natural fracture mapping technique. Through the minimization of human bias in image log analysis, our automated workflow achieves reduced fracture interpretation time and costs while ensuring robust and reproducible results. We demonstrated the efficacy of our approach by applying the workflow to the Illinois Basin-Decatur Project site. The automated workflow successfully identified major fractured zones, multiple baffles, and an interbedded layer with a high resolution of 0.01 ft or 0.12 in. (0.3 cm) and can be upscaled to any desired resolution. Validation through microseismic and image log interpretations allows for accurate and near-real-time mapping of fractures and baffles, significantly enhancing CO 2 pressure forecasting and postinjection site care. Our approach stands out due to its robustness, consistency, and reduced computational cost compared with alternative feature extraction technologies. It presents exciting possibilities for advancing CO 2 sequestration and engineered geothermal efforts by offering comprehensive and efficient fracture mapping solutions. This technology can contribute significantly to the optimization of CO 2 sequestration projects, facilitating sustainable environmental practices, and combating climate change.

Geochemistry & Geophysics↗
NASA NTRS1970

Decoder system Patent

Binary data decoding device for use at receiving end of communication channel

Anderson, T. O.↗
NASA NTRS1983

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗
NASA NTRS2010

Electrically Variable Resistive Memory Devices

Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

Liu, Shangqing↗
DOE OSTI2024

IRIS: Exploring Performance Scaling of the Intelligent Runtime System and its Dynamic Scheduling Policies

High-Performance Computing is becoming increasingly heterogeneous, relying on a diverse mix of hardware to achieve good performance. Paradoxically, current drivers and frameworks for these devices typically require separate languages and implementations for each vendor. Furthermore, there are few tools and little support to schedule codes between these devices in a truly heterogeneous manner-partly because of this fragmentation between vendors and the languages each supports. To overcome both limitations, the Intelligent Runtime System (IRIS) was developed. It allows a common task abstraction to automatically be shared among contemporary vendors and is run from a single host-side API. At runtime, IRIS queries the host system and registers which frameworks and drivers are available, these determine which kernels can be used by the scheduler-CPUs via OpenMP, Nvidia GPUs (CUDA), AMD GPUs (HIP), and Intel and Xilinx FPGAs with OpenCL. IRIS enables tasks to be scheduled to any heterogeneous device and resolves to the appropriate kernel binary at runtimeit only uses the devices supported by the system on which it is run. IRIS supports single-task and graph-based expressions of dependencies of tasks. Additionally, IRIS features a range of dynamic scheduling policies, allowing complex chains of tasks and interactions to be executed, relieving the programmer/user from considering the system to assign tasks to devices optimally. This paper presents the peak performance attainable by IRIS over a range of systems-each with different numbers and types of accelerator devices, it highlights the flexibility of IRIS since these devices are truly heterogeneous, relying on different backends (drivers, frameworks, and languages) which historically required unique implementations to utilize them. We then use this peak performance as a baseline to compare increasingly complex chains of tasks (with increasingly complex task dependencies) and evaluate how IRIS copes. Finally, we consider the performance of different IRIS scheduling policies on this range of task graphs.

Johnston, Beau↗
DOE OSTI2022

Device-Centric Ransomware Detection using Machine Learning-Based Memory Forensics for Smart Inverters

Ransomware attacks are the fastest-growing form of cyberattacks worldwide. Recently, ransomware attacks have targeted industrial control systems (ICSs), including power grids. Lessons learned from recent incidents in ICSs show that ransomware groups can deliver ransomware into not only the organization’s control servers, but also the operational technology (OT) devices such as smart inverters and smart grid devices. This paper proposes a machine learning (ML)- based memory forensics method enabling the detection of ransomware binaries stored in the memory of a commercial smart inverter. Device firmware binary files are extracted from a Serial Peripheral Interface (SPI) flash memory, and samples of both benign and ransomware binaries are generated by a binary manipulation method and a real-world ransomware encryption, separately. A deep transfer learning (DTL) method is used to retrain a convolutional neural network (CNN)-based ransomware detection algorithm using the generated samples. The experimental result validates that the proposed ML-based memory forensics method can accurately detect ransomware files.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

19.28% Efficiency and Stable Polymer Solar Cells Enabled by Introducing an NIR–Absorbing Guest Acceptor

Here, a near-infrared (NIR)-absorbing small-molecule acceptor (SMA) Y-SeNF with strong intermolecular interaction and crystallinity is developed by combining selenophene-fused core with naphthalene-containing end-group, and then as a custom-tailor guest acceptor is incorporated into the binary PM6:L8-BO host system. Y-SeNF shows a 65 nm red-shifted absorption compared to L8-BO. Thanks to the strong crystallinity and intermolecular interaction of Y-SeNF, the morphology of PM6:L8-BO:Y-SeNF can be precisely regulated by introducing Y-SeNF, achieving improved charge-transporting and suppressed non-radiative energy loss. Consequently, ternary polymer solar cells (PSCs) offer an impressive device efficiency of 19.28% with both high photovoltage (0.873 V) and photocurrent (27.88 mA cm –2 ), which is one of the highest efficiencies in reported single-junction PSCs. Notably, ternary PSC has excellent stability under maximum-power-point tracking for even over 200 h, which is better than its parental binary devices. The study provides a novel strategy to construct NIR-absorbing SMA for efficient and stable PSCs toward practical applications.

14 SOLAR ENERGY↗
NASA NTRS1973

High speed direct-binary to binary-coded-decimal converter and scaler

Telemetry (pulse code modulated) digital system usually sends binary numbers representing some parameter that is not value of binary number. Received binary number must be scaled and converted to binary coded decimal to operate readout device to display true value. Group of adders speed up binary number conversion and scaling in one operation.

Toole, P. C.↗
DOE OSTI2023

Improving Cooperative Interactions Between Halogenated Aromatic Additives and Aromatic Side Chain Acceptors for Realizing 19.22% Efficiency Polymer Solar Cells

Processing additive plays an important role in the standard operation procedures for fabricating top performing polymer solar cells (PSCs) through efficient interactions with key photovoltaic materials. However, improving interaction study of acceptor materials to high performance halogenated aromatic additives such as diiodobenzene (DIB) is a widely neglected route for molecular engineering toward more efficient device performances. Here, in this work, two novel Y-type acceptor molecules of BTP-TT and BTP-TTS with different aromatic side chains on the outer positions are designed and synthesized. The resulting aromatic side chains significantly enhanced the interactions between the acceptor molecules and DIB through an arene/halogenated arene interaction, which improved the crystallinity of the acceptor molecules and induced a polymorph with better photovoltaic performances. Thus, high power conversion efficiencies (PCEs) of 18.04% and 19.22% are achieved in binary and ternary blend devices using BTP-TTS as acceptor and DIB as additive. Aromatic side chain engineering for improving additive interactions is proved to be an effective strategy for achieving much higher performance photovoltaic materials and devices.

36 MATERIALS SCIENCE↗
NASA NTRS1978

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

Athale, R. A.↗