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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

The NT digital micro tape recorder

The description of an audio recorder may at first glance seem out of place in a conference which has been dedicated to the discussion of the technology and requirements of mass data storage. However, there are several advanced features of the NT system which will be of interest to the mass storage technologist. Moreover, there are a sufficient number of data storage formats in current use which have evolved from their audio counterparts to recommend a close attention to major innovative introductions of audio storage formats. While the existing analog micro-cassette recorder has been (and will continue to be) adequate for various uses, there are significant benefits to be gained through the application of digital technology. The elimination of background tape hiss and the availability of two relatively wide band channels (for stereo recording), for example, would greatly enhance listenability and speech intelligibility. And with the use of advanced high-density recording and LSI circuit technologies, a digital micro recorder can realize unprecedented compactness with excellent energy efficiency. This is what was accomplished with the NT-1 Digital Micro Recorder. Its remarkably compact size contributes to its portability. The high-density NT format enables up to two hours of low-noise digital stereo recording on a cassette the size of a postage stamp. Its highly energy-efficient mechanical and electrical design results in low power consumption; the unit can be operated up to 7 hours (for continuous recording) on a single AA alkaline battery. Advanced user conveniences include a multifunction LCD readout. The unit's compactness and energy-efficiency, in particular, are attributes that cannot be matched by existing analog and digital audio formats. The size, performance, and features of the NT format are of benefit primarily to those who desire improved portability and audio quality in a personal memo product. The NT Recorder is the result of over ten years of intensive, multi-disciplinary research and development. What follows is a discussion of the technologies that have made the NT possible: (1) NT format mechanics, (2) NT media, (3) NT circuitry and board.

Sasaki, Toshikazu↗
NASA NTRS2003

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Action Potentials/physiology↗
NASA NTRS2012

High-Speed Edge-Detecting Line Scan Smart Camera

A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..

Prokop, Norman F.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRS1990

Digital control of magnetic bearings in a cryogenic cooler

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

Feeley, J.↗
NASA NTRS2008

Performance of MEMS Silicon Oscillator, ASFLM1, under Wide Operating Temperature Range

Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to be offered as commercial-off-the-shelf (COTS) parts by a few companies [1-2]. These quartz-free, miniature silicon devices could compete with the traditional crystal oscillators in providing the timing (clock function) for many digital and analog electronic circuits. They provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [1-2]. In addition, they are encapsulated in compact lead-free packages, cover a wide frequency range (1 MHz to 125 MHz), and are specified, depending on the grade, for extended temperature operation from -40 C to +85 C. The small size of the MEMS oscillators along with their reliability and thermal stability make them candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an ABRACON Corporation MEMS silicon oscillator chip, type ASFLM1, under extreme temperatures.

Patterson, Richard L.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS1993

General-Purpose Driver For Arrays Of Photodetectors

Electronic system containing both digital and analog circuits supplies clock waveforms at frequencies up to 12 MHz and/or bias voltages in 16 output channels. Designed to provide low-noise driving signals for any of variety of arrays of photodetectors. Clock waveform and/or bias in each channel adjusted independently of others to suit requirements of specific array of detectors. System offers primary advantage (adjustability) of prior laboratory systems, but at cost, power, and size like those of prior dedicated, field-deployed systems.

Shu, Peter K.↗
NASA NTRS1993

Circuit and method for producing a flexible reference voltage

A flexible reference voltage circuit includes a circuit for producing a first digital signal representative of a range of reference voltage levels; a circuit for producing a second digital signal representative of a selected reference voltage level within the range of reference voltage levels; an adder for adding the first and second digital signals to produce a third digital signal; and a digital to analog converter for providing an output voltage in response to the third digital signal. The method of producing a flexible reference voltage performed by the circuit is also claimed. The invention can be used with a differential protection circuit to provide a series of trip level ranges, with a series of selectable trip levels in each range. This is accomplished in a high accuracy circuit which is relatively simple to construct, thereby minimizing size and complexity of the current sensor module, in differential protection applications, or the circuitry, if used in a power system controller. Standard digital logic components can be used to perform the necessary range/level decoding.

Thornton, Roger D.↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
NASA NTRS2010

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗
NASA NTRS2002

CMOS foveal image sensor chip

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar↗
NASA NTRS2016

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

Body of Knowledge (BOK)↗
NASA NTRS1989

Electro-optic architecture (EOA) for sensors and actuators in aircraft propulsion systems

Results of a study to design an optimal architecture for electro-optical sensing and control in advanced aircraft and space systems are described. The propulsion full authority digital Electronic Engine Control (EEC) was the focus for the study. The recommended architecture is an on-engine EEC which contains electro-optic interface circuits for fiber-optic sensors on the engine. Size and weight are reduced by multiplexing arrays of functionally similar sensors on a pair of optical fibers to common electro-optical interfaces. The architecture contains common, multiplex interfaces to seven sensor groups: (1) self luminous sensors; (2) high temperatures; (3) low temperatures; (4) speeds and flows; (5) vibration; (6) pressures; and (7) mechanical positions. Nine distinct fiber-optic sensor types were found to provide these sensing functions: (1) continuous wave (CW) intensity modulators; (2) time division multiplexing (TDM) digital optic codeplates; (3) time division multiplexing (TDM) analog self-referenced sensors; (4) wavelength division multiplexing (WDM) digital optic code plates; (5) wavelength division multiplexing (WDM) analog self-referenced intensity modulators; (6) analog optical spectral shifters; (7) self-luminous bodies; (8) coherent optical interferometers; and (9) remote electrical sensors. The report includes the results of a trade study including engine sensor requirements, environment, the basic sensor types, and relevant evaluation criteria. These figures of merit for the candidate interface types were calculated from the data supplied by leading manufacturers of fiber-optic sensors.

Glomb, W. L., Jr.↗
NASA NTRS2004

Magnetohydrodynamic and Paramagnetic Phenomena in Electrochemistry with Diamagnetic and Ferromagnetic Millielectrodes

There are three kinds of body forces operating in electrolytic solutions in the magnetic field: the magnetohydrodynamic force F(sub B) (=i x B), the F(sub delB) force (approximately B(raised dot)gradB) and the F(sub delC) force (approximately |B|(sup 2)gradC). These three forces manifest themselves differently, depending on the experimental conditions. Thus, diamagnetic disc millielectrodes (e.g., Au) with their plane parallel to the flux density of the homogeneous magnetic field of an electromagnet yield convective behavior analogous to that observed with rotating electrodes; that response is controlled by F(sub B). The same electrodes placed in the inhomogeneous field of a strong permanent magnet yield also convective behavior that is controlled by both F(sub B) and F(sub delB). Finally, similarly sized millielectrodes made of permanent magnets (e.g., Au-coated Nd-Fe-B discs) yield diffusion-controlled behavior at conditions where a gold disc electrode shows behavior dominated by density gradient driven natural convection; in this case the predominant forces are both F(sub delB) and F(sub delC). Under open circuit conditions, ferromagnetic (i.e., magnetizable) millielectrodes (Co, Fe, Ni) dipped in corrosive solutions and placed in homogeneous magnetic fields yield mass-transfer phenomena that seem to be controlled by magnetophoresis.

Leventis, Nicholas↗
NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗
NASA NTRS2001

System Miniaturization Via Heterogeneous Integration of Electronic Devices for Deep Space Missions

The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.

DelCastillo, L.↗
NASA NTRSDate not supplied

Simulated Ball Lightning on A Submarine

Silberg (1962) discusses the observation of a ball-shaped glowing plasma (labeled a “plasmoid”) that occurred aboard a diesel-electric submarine when the switchgear opened a circuit carrying a current of 156,000 amps. In 1968 joint NASA/Navy experiments were conducted for an analogous situation aboard a similar submarine to characterize the plasmoids and to determine if they were reproducible with more modest electrical currents. Movies and spectra were obtained for approximately 40 arc events. Several events showed the presence of clouds of glowing gas as well as small plasmoids. The plasmoids had diameters of several mm that lasted approximately 0.2 seconds. Spectra of the initiating arcs showed the presence of emission lines from atomic copper and silver from the electrodes as well as those from singly excited oxygen and nitrogen atoms. Peak currents of several kiloamps were measured. Graphs of the time-histories of plasmoid motion, size, relative color ratios, and relative optical flux will be shown for two plasmoids.

plasma↗