Results for “analog circuit sizing” — Page 2

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’ for Rapid Support of Low-TRL and Educational Payloads: A Software-Configured EPS Combined with Flexible C&DH

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Spacecraft↗

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Avery Brock↗

NASA NTRS2013

High-Speed, High-Resolution Time-to-Digital Conversion

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Katz, Richard↗

NASA NTRS1991

Programmable digital modem

The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips.

Poklemba, John J.↗

DOE OSTI2024

Training self-learning circuits for power-efficient solutions

As the size and ubiquity of artificial intelligence and computational machine learning models grow, the energy required to train and use them is rapidly becoming economically and environmentally unsustainable. Recent laboratory prototypes of self-learning electronic circuits, such as “physical learning machines,” open the door to analog hardware that directly employs physics to learn desired functions from examples at a low energy cost. In this work, we show that this hardware platform allows for an even further reduction in energy consumption by using good initial conditions and a new learning algorithm. Using analytical calculations, simulations, and experiments, we show that a trade-off emerges when learning dynamics attempt to minimize both the error and the power consumption of the solution—greater power reductions can be achieved at the cost of decreasing solution accuracy. Finally, we demonstrate a practical procedure to weigh the relative importance of error and power minimization, improving the power efficiency given a specific tolerance to error.

Stern, Menachem (ORCID:0000000302158082)↗

DOE OSTI2021

Approximate Bacon-Shor code and holography

We explicitly construct a class of holographic quantum error correction codes with non-trivial centers in the code subalgebra. Specifically, we use the Bacon-Shor codes and perfect tensors to construct a gauge code (or a stabilizer code with gauge-fixing), which we call the holographic hybrid code. This code admits a local log-depth encoding/decoding circuit, and can be represented as a holographic tensor network which satisfies an analog of the Ryu-Takayanagi formula and reproduces features of the sub-region duality. We then construct approximate versions of the holographic hybrid codes by “skewing” the code subspace, where the size of skewing is analogous to the size of the gravitational constant in holography. These approximate hybrid codes are not necessarily stabilizer codes, but they can be expressed as the superposition of holographic tensor networks that are stabilizer codes. For such constructions, different logical states, representing different bulk matter content, can “back-react” on the emergent geometry, resembling a key feature of gravity. The locality of the bulk degrees of freedom becomes subspace-dependent and approximate. Such subspace-dependence is manifest from the point of view of the “entanglement wedge” and bulk operator reconstruction from the boundary. Exact complementary error correction breaks down for certain bipartition of the boundary degrees of freedom; however, a limited, state-dependent form is preserved for particular subspaces. We also construct an example where the connected two-point correlation functions can have a power-law decay. Coupled with known constraints from holography, a weakly back-reacting bulk also forces these skewed tensor network models to the “large N limit” where they are built by concatenating a large N number of copies.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS1995

Silicon Satellites: Picosats, Nanosats, and Microsats

Silicon, the most abundant solid element in the Earth's lithosphere, is a useful material for spacecraft construction. Silicon is stronger than stainless steel, has a thermal conductivity about half that of aluminum, is transparent to much of the infrared radiation spectrum, and can form a stable oxide. These unique properties enable silicon to become most of the mass of a satellite, it can simultaneously function as structure, heat transfer system, radiation shield, optics, and semiconductor substrate. Semiconductor batch-fabrication techniques can produce low-power digital circuits, low-power analog circuits, silicon-based radio frequency circuits, and micro-electromechanical systems (MEMS) such as thrusters and acceleration sensors on silicon substrates. By exploiting these fabrication techniques, it is possible to produce highly-integrated satellites for a number of applications. This paper analyzes the limitations of silicon satellites due to size. Picosatellites (approximately 1 gram mass), nanosatellites (about 1 kg mass), and highly capable microsatellites (about 10 kg mass) can perform various missions with lifetimes of a few days to greater than a decade.

Janson, Siegfried W.↗

NASA NTRS2009

Assessment of Operation of EMK21 MEMS Silicon Oscillator Over Wide Temperature Range

Electronic control systems, data-acquisition instrumentation, and microprocessors require accurate timing signals for proper operation. Traditionally, ceramic resonators and crystal oscillators provided this clock function for the majority of these systems. Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to surface as commercial-off-the-shelf (COTS) parts by a few companies. These quartz-free, miniature silicon devices could easily replace the traditional crystal oscillators in providing the timing/clock function for many digital and analog circuits. They are reported to provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [ 1-2]. In addition, they are encapsulated in compact lead-free packages and cover a wide frequency range (1 MHz to 125 MHz). The small size of the MEMS oscillators along with their thermal stability make them ideal candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an Ecliptek Corporation MEMS silicon oscillator chip under extreme temperatures.

Patterson, Richard L.↗

NASA NTRS1993

The NT digital micro tape recorder

The description of an audio recorder may at first glance seem out of place in a conference which has been dedicated to the discussion of the technology and requirements of mass data storage. However, there are several advanced features of the NT system which will be of interest to the mass storage technologist. Moreover, there are a sufficient number of data storage formats in current use which have evolved from their audio counterparts to recommend a close attention to major innovative introductions of audio storage formats. While the existing analog micro-cassette recorder has been (and will continue to be) adequate for various uses, there are significant benefits to be gained through the application of digital technology. The elimination of background tape hiss and the availability of two relatively wide band channels (for stereo recording), for example, would greatly enhance listenability and speech intelligibility. And with the use of advanced high-density recording and LSI circuit technologies, a digital micro recorder can realize unprecedented compactness with excellent energy efficiency. This is what was accomplished with the NT-1 Digital Micro Recorder. Its remarkably compact size contributes to its portability. The high-density NT format enables up to two hours of low-noise digital stereo recording on a cassette the size of a postage stamp. Its highly energy-efficient mechanical and electrical design results in low power consumption; the unit can be operated up to 7 hours (for continuous recording) on a single AA alkaline battery. Advanced user conveniences include a multifunction LCD readout. The unit's compactness and energy-efficiency, in particular, are attributes that cannot be matched by existing analog and digital audio formats. The size, performance, and features of the NT format are of benefit primarily to those who desire improved portability and audio quality in a personal memo product. The NT Recorder is the result of over ten years of intensive, multi-disciplinary research and development. What follows is a discussion of the technologies that have made the NT possible: (1) NT format mechanics, (2) NT media, (3) NT circuitry and board.

Sasaki, Toshikazu↗

NASA NTRS2003

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Action Potentials/physiology↗

DOE OSTI2026

Digital Silicon Photomultiplier Chip Testing

Silicon Photomultipliers (SiPMs) are highly sensitive photodetectors. Traditional analog SiPMs require complex external readout electronics. Digital SiPMs (dSiPMs) include digital readout circuitry directly on-chip, offering superior timing resolution, reduced power consumption and compact size, pixel-level masking for active noise reduction. The primary objectives of this study are to, verify digital logic integrity of the shift registers used for controlling the pixel masking circuit, and determine the dark count rate of individual pixels as a function of bias voltage and clock frequency. I observe and explain behavior of the shift register and counting circuit.

Graham, Bennett [U. Chicago (main)]↗

NASA NTRS2012

High-Speed Edge-Detecting Line Scan Smart Camera

A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..

Prokop, Norman F.↗

NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗

DOE OSTI2020

Quantum neuromorphic computing

Quantum neuromorphic computing physically implements neural networks in brain-inspired quantum hardware to speed up their computation. In this perspective article, we show that this emerging paradigm could make the best use of the existing and near future intermediate size quantum computers. Some approaches are based on parametrized quantum circuits and use neural network-inspired algorithms to train them. Other approaches, closer to classical neuromorphic computing, take advantage of the physical properties of quantum oscillator assemblies to mimic neurons and synapses to compute. In this work, we discuss the different implementations of quantum neuromorphic networks with digital and analog circuits, highlight their respective advantages, and review exciting recent experimental results.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Porphene and porphite as porphyrin analogs of graphene and graphite

Two-dimensional materials have unusual properties and promise applications in nanoelectronics, spintronics, photonics, (electro)catalysis, separations, and elsewhere. Most are inorganic and their properties are difficult to tune. Here we report the preparation of Zn porphene, a member of the previously only hypothetical organic metalloporphene family. Similar to graphene, these also are fully conjugated two-dimensional polymers, but are composed of fused metalloporphyrin rings. Zn porphene is synthesized on water surface by two-dimensional oxidative polymerization of a Langmuir layer of Zn porphyrin with K 2 IrCl 6 , reminiscent of known one-dimensional polymerization of pyrroles. It is transferable to other substrates and bridges μm-sized pits. Contrary to previous theoretical predictions of metallic conductivity, it is a p-type semiconductor due to a predicted Peierls distortion of its unit cell from square to rectangular, analogous to the appearance of bond-length alternation in antiaromatic molecules. The observed reversible insertion of various metal ions, possibly carrying a fifth or sixth ligand, promises tunability and even patterning of circuits on an atomic canvas without removing any π centers from conjugation.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗

NASA NTRS1990

Digital control of magnetic bearings in a cryogenic cooler

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

Feeley, J.↗

NASA NTRS2008

Performance of MEMS Silicon Oscillator, ASFLM1, under Wide Operating Temperature Range

Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to be offered as commercial-off-the-shelf (COTS) parts by a few companies [1-2]. These quartz-free, miniature silicon devices could compete with the traditional crystal oscillators in providing the timing (clock function) for many digital and analog electronic circuits. They provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [1-2]. In addition, they are encapsulated in compact lead-free packages, cover a wide frequency range (1 MHz to 125 MHz), and are specified, depending on the grade, for extended temperature operation from -40 C to +85 C. The small size of the MEMS oscillators along with their reliability and thermal stability make them candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an ABRACON Corporation MEMS silicon oscillator chip, type ASFLM1, under extreme temperatures.

Patterson, Richard L.↗