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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2

A Scalable & Non-Destructive Characterization Strategy to Study Semiconductor/Dielectric Interfaces and Predict Wafer-Level Device Performance

The defect density present at the dielectric-semiconductor interface in an MOS structure directly influences the channel carrier characteristics in semiconductor devices, especially in wide bandgap material systems used in power devices. While these trap defects are typically quantified through electrical characterization of MOS-capacitor test structures, this treatment offers very little insight into the physical nature of interface defects. Such shortcomings demand a physical characterization strategy to guide fabrication optimization. X-ray photoelectron spectroscopy (XPS) is suggested as a viable technique to determine chemical data for dielectric interfaces formed using atomic layer deposition (ALD) on GaN substrates. Previously, 1-D XPS characterization has confirmed the presence of a Ga x O y interlayer between ALD dielectrics and the GaN substrate. In this work, XPS data is serially collected to form 2-D images of an ALD-Al 2 O 3 /GaN interface as a proof-of-concept experiment for in-situ XPS quality monitoring during ALD processing. The information provided by this work reveals some of the challenges for incorporating XPS characterization as an in-situ strategy during fabrication of GaN-based devices. Separately, electrical mapping of a 2-D array of ALD-Al 2 O 3 /GaN MOS-capacitor devices provide a means to quantify the spatial variations in interface quality across a single wafer. Physical characterization techniques, such as time-of-flight secondary ion mass spectroscopy, provide additional chemical information about the Al 2 O 3 /Ga x O y /GaN structure that complement the electrical mapping results. This analysis shows that a higher Ga x O y content correlates with higher interface state defects for trap energies deep in the band gap.

42 ENGINEERING

Sonic Wafering of III-V substrates for High Efficiency Cells: A path to <$0.50/W

This project developed and demonstrated Sonic Lift-off, a novel technology that enables the reuse of expensive semiconductor substrates used to manufacture high-efficiency solar cells. By using sound waves to precisely separate thin layers of material, the process significantly reduces manufacturing costs while maintaining the performance of advanced III–V solar cells. These solar cells are among the most efficient in the world and are used in space, aerospace, and emerging terrestrial applications. The results of this work show that substrate reuse can be achieved without degrading device performance, offering a pathway to more affordable, high-performance solar technologies. This advancement supports U.S. clean energy goals by enabling broader deployment of renewable energy systems and strengthening domestic manufacturing capabilities in advanced photovoltaics.

14 SOLAR ENERGY

System and method for bending crystal wafers for use in high resolution analyzers

The invention provides a method for fabricating analyzers, the method comprising providing a radiation manipulating material on a first surface of a flexible support; contacting a second surface of the flexible support to a permeable mold, wherein the mold has a first flexible support contact surface and a second surface; and applying negative pressure to the second side of the flexible support to cause the flexible support to conform to the first flexible support contact surface of the mold. Also provided is a system for fabricating crystal analyzers, the system comprising crystal structures reversibly attached to a flexible support; a porous mold reversibly contacting the flexible support, wherein the mold defines a topography; and a negative pressure applied to the flexible support to cause the crystal structures to conform to the topography.

Said, Ayman H.

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination. Here, in this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

42 ENGINEERING

Low embodied energy and carbon, high lifetime silicon boules via a combined chemical vapor deposition/float zone process

This work evaluates a new process route to making float zone (Fz)-quality silicon wafers using a combination of computational fluid dynamics (CFD) modeling and technoeconomic analysis. Our analysis finds that the new process competes with Czochralski (Cz)-grown wafers on a levelized cost of energy system level. The new process also decreases embodied energy and carbon of silicon photovoltaics (PV) by ~6x circumventing the energy-costly Siemens process used in polycrystalline silicon (poly-Si) production plants to generate feedstock for Fz and Cz boules. Instead of using poly-Si from the Siemens process to feed crystallization, the new process uses the high-purity, trichlorosilane (TCS) precursor gas to grow a poly-Si feed rod in-situ during a modified Fz1,2 boule growth process. The gas-to-boule float zone process enables opportunity to produce high-purity (low metals and oxygen content), uniformly doped single crystal silicon boules and wafers with high bulk lifetimes (τ bulk > 15 ms) to enable higher efficiency cells (>27 %) with fewer known degradation mechanisms than Czochralski (Cz)-grown wafers. These benefits reduce the levelized cost of electricity (LCOE) of PV-produced electricity. Here we show the results of our CFD and chemical modeling of the process to prove feasibility and economic viability.

14 SOLAR ENERGY

A Path to III-V Photovoltaic Cost Reduction Combining GaAs (211) Spalling with Halide Vapor Phase Epitaxy

This presentation is an overview of the following, Spalling on 211 oriented wafers produces flat surface without faceting: 1) Demonstrated spall on entire 2" wafer; 2) GaAs and GaInP grown on 211 wafers by HVPE; and 3) Promising cell with VOC=1.02 V and IQE-1. Next steps: 1) Grow cell on spalled wafer and 2) Growth studies to improve material and cell on 211 substrates.

14 SOLAR ENERGY

Quality assurance and quality control of the $26~\text {m}^2$ SiPM production for the DarkSide-20k dark matter experiment

DarkSide-20k is a novel liquid argon dark matter detector currently under construction at the Laboratori Nazionali del Gran Sasso (LNGS) of the Istituto Nazionale di Fisica Nucleare (INFN) that will push the sensitivity for Weakly Interacting Massive Particle (WIMP) detection into the neutrino fog. The core of the apparatus is a dual-phase Time Projection Chamber (TPC), filled with 50 tonnes of low radioactivity underground argon (UAr) acting as the WIMP target. NUV-HD-cryo Silicon Photomultipliers (SiPM)s designed by Fondazione Bruno Kessler (FBK) (Trento, Italy) were selected as the photon sensors covering two $10.5~\text {m}^2$ Optical Planes, one at each end of the TPC, and a total of $5~\text {m}^2$ photosensitive surface for the liquid argon veto detectors. This paper describes the Quality Assurance and Quality Control (QA/QC) plan and procedures accompanying the production of FBK NUV-HD-cryo SiPM wafers manufactured by LFoundry s.r.l. (Avezzano, AQ, Italy). SiPM characteristics are measured at 77 K at the wafer level with a custom-designed probe station. As of March 2025, 1314 of the 1400 production wafers (94% of the total) for DarkSide-20k were tested. The wafer yield is $93.2\pm 2.5$%, which exceeds the 80% specification defined in the original DarkSide-20k production plan.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics

Resistivity distribution and donor properties of antimony-doped n -type Czochralski silicon ingots

We investigate antimony (Sb)-doped Czochralski-grown silicon as an alternative n-type substrate for photovoltaic applications, and characterize their axial resistivity distribution, donor properties, and mechanical strength. We find that Sb-doped ingots can achieve a more uniform resistivity distribution along the axial direction compared to P-doped counterparts. Dopant concentration profiles in P-doped ingots can be accurately modelled using the standard Scheil's equation, accounting only for dopant segregation during solidification. In contrast, modelling Sb-doped ingots requires consideration of both dopant segregation and evaporation effects to fit the dopant distribution accurately. Using electron paramagnetic resonance spectroscopy at 9 K, we observe two hyperfine lines in P-doped samples, and six hyperfine lines for Sb 121 and eight for Sb 123 isotopes, with the number of hyperfine lines governed by the nuclear spins. We further identify two-atom Sb clustering in the Sb-doped wafers, confirmed through simulations of the additional weak electron paramagnetic resonance peaks. Finally, we find that 140 μm as-cut planar Sb-doped wafers exhibit slightly higher mechanical strength compared to P-doped wafers.

14 SOLAR ENERGY