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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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35 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
DOE OSTI2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗
DOE OSTI2025

Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)

4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.

42 ENGINEERING↗
DOE OSTI2026

Gallium Arsenide Semiconductor Opening Switches: Enabling Nanosecond High Powering Pulsed Systems

The goal of this work awas to investigate design manufacturing semiconductor opening switches (SOS) in both silicon and gallium arsenide (GaAs). Solid-state opening switches are critical components for pulsed power systems and applications in directed energy, dielectric wall accelerators, and novel semiconductor manufacturing techniques. Under this funding, we have developed silicon SOS designs that suppresses an unwanted prepulse, increases the peak output voltage by about 10 percent, and reduces the pulse rise time by ~ 4x compared with more conventional profiles. Through this effort we have improved device fabrication and bonding techniques. Additionally, work on this the GaAs opening switch has defined a unique application space that these devices are suited for. GaAs opening switches have short risetimes and pulse widths compared to silicon devices, however the short carrier lifetime of GaAs makes the circuit design more challenging than in silicon. For high PRF operation, the lifetime of the GaAs is an advantage compared to silicon. TCAD simulations of GaAs devices have been used to optimize a GaAs profile. Additionally, we have designed pulsers with sub 50ns reserve pump times and tested GaAs COTs PIN diodes in them.

42 ENGINEERING↗
DOE OSTI2021

Simulation and Modeling of Time-Resolved X-Ray Detector for the Saturn Accelerator

In this work, we present the technology-aided computer design (TCAD) device simulation and modeling of a silicon p-i-n diode for detecting time-dependent X-ray radiation. We show that the simulated forward and reverse breakdown current–voltage characteristics agree well with the measured data under nonradiation environment by only calibrating carrier lifetimes for the forward bias case and avalanche model critical fields for the reverse bias condition. Using the calibrated parameters and other nominal material properties, we simulated the radiation responses of the p-i-n diode and compared with experimental data when the diode was exposed to X-ray radiation at Sandia’s Saturn facility and the Idaho State University (ISU) TriMeV facility. For Saturn’s Gaussian dose-rate pulses, we show three findings from TCAD simulations. First, the simulated photocurrents are in excellent agreement with the measured data for two dose-rate pulses with peak values of 1.16×10 10 and 1.88×10 10 rad(Si)/s. Second, the simulation results of high dose-rate pulses predict increased delayed photocurrents with longer time tails in the diode electrical responses due to excess carrier generation. Third, simulated peak values of diode radiation responses versus peak dose rates at different bias conditions provide useful guidance to determine the dose-rate range that the p-i-n diode can reliably detect in experiment. For TriMeV’s non-Gaussian dose-rate pulse, our simulated diode response is in decent agreement with the measured data without further calibration. We also studied the effects of device geometry, recombination process, and dose-rate enhancement via TCAD simulations to understand the higher measured response in the time after the peak dose-rate radiation for the p-i-n diode exposed to TriMeV irradiation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Evaluation of radiation hardness of High-Voltage silicon vertical JFETs

In the future ATLAS Inner Tracker, each silicon strip module will be equipped with a switch able to separate the high voltage supply from the sensor in case the latter becomes faulty. The switch, placed in between the HV supply and the sensor, needs to sustain a high voltage in its OFF state, to offer a low resistance path for the sensor leakage current in the ON state, and be radiation hard up to 1.2 * 10 15 neq/cm 2 along with other requirements. While GaN JFETs have been selected as suitable rad-hard switch, a silicon vertical HV-JFET was developed by Brookhaven National Laboratory as an alternative option. Pre-irradiation results showed the functionality of the device and proved that the silicon HV-JFET satisfied the pre-irradiation requirements for the switch. To assess its suitability after irradiation, a few p-type HV-JFETs have been neutron irradiated at Jozef Stefan Institute (JSI, Ljubljana, Slovenia). Overall, this paper reports the static characterization of these irradiated devices and the TCAD numerical simulations used to get an insight of the physics governing the post-irradiation behaviour.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

HPC4Mfg with Samsung: Making semiconductor devices cool through HPC ab initio simulations

For decades, the semiconductor technology has followed the Moore’s law, making newer devices more powerful and energy efficient. Recently, however, it has reached a point where the performance and the energy efficiency of the device do not improve with the shrinking device size. One of the fundamental reasons of this deviation from the past trend is the interconnect resistance, which becomes larger with the shrinking size. The devices size is so small that the quantum mechanical effects can no longer be ignored and the traditional continuum simulation tools such as TCAD become inadequate. In this project, Samsung Semiconductor Inc. and Lawrence Berkeley National Laboratory has collaborated to perform first of kind device-scale ab initio simulations to optimize materials and interconnect morphology to minimize interconnect resistance. We have tested the use of LS3DF method and the PEtot_trans approach on top of the folded spectrum method (FSM) Escan code to calculate the scattering state, and to study various effects influence the interconnect conductivity. We found that, the LS3DF can be used to calculate such metallic system. On the other hand, the use of Escan code to solve the linear equation is not practical due to the slow convergence. We have implemented a Chebyshev filter technique to calculate a few hundred eigen states near the scattering state energy E, then use these eigen states as preconditioner to solve the linear equation. We have used this approach to study the different factors which affect the interconnect conductivity, including the shape, the point defect, the temperature, and the grain boundary.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Synchrotron light source X-ray detection with Low-Gain Avalanche Diodes

Abstract Low Gain Avalanche Diodes (LGADs) represent the state-of-the-art in timing measurements and will instrument the future Timing Detectors of ATLAS and CMS for the High-Luminosity LHC. While initially conceived as a sensor for charged particles, the intrinsic gain of LGADs makes it possible to detect low-energy X-rays with good energy resolution and excellent time resolution (tens of picoseconds). Using the Stanford Synchrotron Radiation Lightsource (SSRL) at SLAC, several LGADs designs were characterized with energies from 5 to 70 keV. The SSRL provides 10 ps pulsed X-ray bunches separated by 2 ns intervals with an energy dispersion (ΔE/E) of 10 -4 . LGADs from Hamamatsu Photonics (HPK) and Brookhaven National Laboratory (BNL) with different thicknesses ranging from 20 μm to 50 μm and different gain layer designs were read out using fast amplification boards and digitized with a high bandwidth and high sampling rate oscilloscope. PIN devices from HPK and AC-LGADs from BNL were characterized as well. A systematic and detailed characterization of the devices' energy linearity, resolution, and time resolution as a function of X-ray energy was performed for different biasing voltages at room temperature and are reported in this work. The charge collection and multiplication mechanism were simulated using Geant4 and TCAD Sentaurus, providing an important handle for interpreting the data.

Instruments & Instrumentation↗
DOE OSTI2026

Studying AC-LGAD strip sensors from laser and testbeam measurements

Here, this paper presents the setup assembled to characterize and measure the spatial and timing resolutions of AC-coupled Low Gain Avalanche Diodes (AC-LGADs), using a 1060 nm laser source to deposit initial charges with a defined calibration methodology. The results were compared to those obtained with a 120 GeV proton beam. Despite the differences in the charge deposition mechanism between the laser and proton beam, the spatial and temporal resolutions were found to be compatible between the two sources after calibration. With 4D tracking detectors expected to play a vital role in upcoming collider experiments, we foresee this work as a way to evaluate the performance of semiconductor sensors that can augment testbeam measurements and accelerate R&D efforts. Additionally, simulation studies using Silvaco TCAD and Weightfield2 were carried out to understand the various contributing factors to the total time resolution in AC-LGAD sensors, measured using the laser source.

FOS: Physical sciences↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2022

Gallium Nitride Superjunction Transistor (Continued Funding Report)

The initial goal of this project is to develop the gallium vacancy assisted diffusion (GAID) method in GaN and apply it to demonstrate 2-terminal, 3-terminal, and large area Superjunction-enhanced modules. These devices will find use in high efficiency power conversion applications with the capability of operating at higher voltages, higher frequency, and less loss than comparable stat-ofthe-art devices. The approach of this project has been to utilize simulation tools to drive diffusion experiments and inform semiconductor device fabrication processes. VASP has been relied upon to simulate first principles diffusion mechanisms while SILVACO TCAD has been utilized to understand tradeoffs of the the critical dimensions in GaN devices.

42 ENGINEERING↗
DOE OSTI2024

Coupled Process/Device Modeling and Point Defect Engineering of Cu(In,Ga)Se 2 Solar Cells

Point defects directly impact solar cell device performance by limiting the carrier lifetime. In this work, density functional theory calculations are first used to determine the formation energy and diffusion energy barriers of dominant defects in Cu(In,Ga)Se 2 . Next, continuum reaction–diffusion models are developed to analyze the redistribution of defects during manufacturing processes. We estimate defect capture cross sections using a first-principles-based approach. Here, these cross sections are combined with our calculated defect profiles and trap energy levels to parameterize a Shockley–Read–Hall recombination model, which we implement into a device simulator to predict carrier lifetimes and device performance. In that way, a predictive technology computer aided design model is built to predict and optimize the performance of Cu(In,Ga)Se 2 solar cells.

14 SOLAR ENERGY↗
DOE OSTI2024

CIGS Technology Advancement via Fundamental Modeling of Defect/Impurity Interactions (Final Technical Report)

The primary goals of the proposed work were to provide modeling tools (and the associated insight which comes along with model development) for design and optimization of CuIn x Ga 1-x Se 2 (CIGS) and CdSeTe (CST) solar cell manufacturing processes and to establish the foundation for comprehensive end-to-end predictive modeling tools to enable optimization of thin film photovoltaic technology for performance, cost, yield, and reliability. The initial focus of efforts within this project was to develop coupled process/optical/device models for CIGS PV technology and to work with Siva Power to apply that TCAD (technology computer-aided design) system to improve the efficiency and reduce manufacturing costs for CIGS solar cells. Our approach to that end was to generate an extensive database of DFT calculations and to use those calculations via statistical thermodynamics methods and Monte Carlo simulation to develop and characterize models for the behavior of native defects as well as intentional and unintentional impurities, including the redistribution of the primary components of CIGS films. Increased effort went toward coupling those models for defect behavior and composition evolution to the performance of multicrystalline CIGS solar cells via prediction of doping level and recombination lifetime as function of manufacturing process. In the second budget period, the project pivoted to developing a similar system for the CdSeTe system, focused especially on understanding the role of Se/Te alloy concentration. Execution of the project resulted in the successful development of TCAD systems for both CIGS and CdSeTe thin film PV within the Synopsys Sentaurus framework by utilizing the Alagator interface. In the first budget period of the project, we developed quantitative models for the major components of CIGS PV and implemented them within a framework that couples process, optical, and device simulation. From the insights we have gained, we identified novel opportunities for enhancing CIGS solar cell performance and have laid the groundwork to further optimize the layer structure, composition profile, and thermal cycles for substantially improved efficiency and lower manufacturing costs. For the CIGS system, process changes to achieve greater than 1% absolute enhancement in efficiency were identified, but testing of those approaches was stymied by lack of a domestic CIGS manufacturing partner after the closure of Siva Power as well as Miasole. For CdSeTe, a fully capable TCAD system only became ready to apply near the end of the project period, so substantial opportunities remain to apply those models to enhance the leading thin film PV technology.

14 SOLAR ENERGY↗
DOE OSTI2021

Double Sided LGAD Design Studies

We summarize TCAD design studies for double sided thick buried layer Low Gain Avalanche Diodes (LGADs). These thick double sided devices introduce new features that require overall optimization. We describe both the parameterized and full process simulation and discuss how the results affect the range of process and LGAD physical parameters.

74 ATOMIC AND MOLECULAR PHYSICS↗