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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Porous silicon carbide (SiC) semiconductor device

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Shor, Joseph S.↗
NASA NTRS2004

LERCIP 2004 Summary

This summer I am continuing my project from the previous two summers. My work involves ohmic contacts to N-type silicon carbide (Sic) devices. My mentor, Dr. Robert Okojie, is developing the technology behind high performance sensors and actuators for harsh environments. Sic is useful because it is able to operate at temperatures up to 600 C and it is resistant to radiation damage. This allows sensors and electronics to be placed in new locations, such as inside a jet engine or in space application without using heavy shielding. Ultimately this results in more efficient, smarter engine technology, reduced launch weights for spacecraft, and high power and high temperature electronics. A fundamental part of Sic devices is the ohmic contact. The contact is the interface between the semiconductor (Sic) and external circuitry. The current flowing in and out the devices is through the contact. Ensuring that these contacts remain ohmic (linear I-V behavior) allows us to fabricate devices that do not waste power at the metallurgical junction. Another key part is maintaining a low contact resistance. It is desired to maintain minimum energy loss by avoiding a rectifying electrical characteristic. My project is to develop and implement a testing procedure for measuring the contact resistance while the device is operating at high temperature. It is important to measure the contacts while simulating the true operating environment as closely as possible. For this reason, measurements are taken while the device is heated at intervals up to 600 C in air. To test the long tern reliability of the devices, the high temperature measurements are repeated after heating the sample for long intervals in air. A new set of data is gathered after heating for a total of 100, 200 and then 400 hours. The current as a function of voltage and the contact resistance was measured using the four point probe technique. The four point probe method is chosen because it measures contact resistance while eliminating error due to wire resistance and calibration issues.

DeAngelis, David↗
DOE OSTI2024

A Low-Profile Gate Power Supply for a SiC Phase Leg with Reduced Isolation Capacitance

Gate driver power supply (GDPS) for SiC devices needs power to 5 W as the switching frequency increases to hundreds of kHz. Resonant converters with planar magnetics demand GDPS with a lower profile. Also, the isolation capacitance (Cp) needs to be minimized for SiC devices with high dv/dt. This paper proposed a planar 5 W*2, 20 V isolated gate power supply for a SiC phase leg in the EV traction inverter. Air-core magnetics with PCB windings are applied for low profile. A single-switch resonant Class-E topology is proposed with zero-voltage switching at 6.78 MHz to minimize the magnetics footprint for a 6 pF Cp. Compared with commercial power supplies with similar power, the proposed power supply reduced the profile and Cp by more than half without sacrificing its efficiency and power density.

Li, Bo↗
NASA NTRS2001

Electro-Thermal Simulation Studies of SiC Junction Diodes Containing Screw Dislocations Under High Reverse-Bias Operation

The objective of this work was to conduct a modeling study of SiC P-N junction diodes operating under high reverse biased conditions. Analytical models and numerical simulation capabilities were to be developed for self-consistent electro-thermal analysis of the diode current-voltage (I-V) characteristics. Data from GRC indicate that screw dislocations are unavoidable in large area SiC devices, and lead to changes in the SiC diode electrical response characteristics under high field conditions. For example, device instability and failures linked to internal current filamentation have been observed. The physical origin of these processes is not well understood, and quantitative projections of the electrical behavior under high field and temperature conditions are lacking. Thermal calculations for SiC devices have not been reported in the literature either. So estimates or projections of peak device temperatures and power limitations do not exist. This numerical study and simulation analysis was aimed at resolving some of the above issues. The following tasks were successfully accomplished: (1) Development of physically based models using one- and two-dimensional drift-diffusion theory for the transport behavior and I-V characteristics; (2) One- and two-dimensional heat flow to account for internal device heating. This led to calculations of the internal temperature profiles, which in turn, were used to update the electrical transport parameters for a self-consistent analysis. The temperature profiles and the peak values were thus obtainable for a given device operating condition; (3) Inclusion of traps assumed to model the presence of internal screw dislocations running along the longitudinal direction; (4) Predictions of the operating characteristics with and without heating as a function of applied bias with and without traps. Both one and two-dimensional cases were implemented; (5) Assessment of device stability based on the operating characteristics. The presence of internal non-uniformities, particularly filamentary structures, was probed and demonstrated; (6) Cause and physical origins of filamentary behavior and unstable I-V characteristics were made transparent; (7) It was demonstrated that diodes containing defects would be more prone to thermal breakdown associated with the temperature dependent decrease in the thermal conductivity; and (8) Finally, negative differential resistance (S-shaped NDR) which can potential lead to device instability and filamentary behavior was shown to occur for diodes containing a line of defects such as could be associated with a screw dislocation line.

Joshi, R. P.↗
DOE OSTI2023

Power Conversion Systems Enabled by SiC BiDFET Device

The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. Furthermore, the matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac-ac and ac dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

42 ENGINEERING↗
NASA NTRS1989

Microwave and millimeter-wave power generation in silicon carbide (SiC) IMPATT devices

There are two points that should be noted. First, in the thermal resistance calculations it is assumed that the device is operating at 773 K while the results of the room temperature simulations are used. This was done because there is not enough information to correctly predict the material parameters at 773 K. Since, in general, device performance degrades with increasing temperature, the cw results are perhaps a bit optimistic. Second, the electric field in these structures gets extremely high and there might be some possibility of tunneling. This was not incorporated into the simulation. Again, this could result in different device operating conditions.

Mehdi, I.↗
NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗
NASA NTRS2003

Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers

Most SiC devices are implemented in homoepitaxial films grown on 4H/6H-SiC wafers with surfaces 3 degrees to 8 degrees off-axis from the (0001) basal plane. This approach has not prevented many substrate crystal defects from propagating into SiC epilayers, and does not permit the realization of SiC heteropolytype devices. This presentation describes recent advances in SiC epitaxial growth that begun to overcome the above shortcomings for arrays of mesas patterned into on-axis 4H/6H-SiC wafers. First, we demonstrated that atomic-scale surface steps can be completely eliminated from 4H/6H-SiC mesas via on-axis homoepitaxial step-flow growth, forming (0001) basal plane surfaces (up to 0.4 mm x 0.4 mm) for larger than previously thought possible. Step-free surface areas were then extended by growth fo thin lateral cantilevers from the mesa tops. These lateral cantilevers enabled substrate defects to be reduced and relocated in homoepitaxial films in a manner not possible with off-axis SiC growth. Finally, growth of vastly improved 3C-SiC heterofilms was achieved on 4H/6H-SiC mesas using the recently develop step-free surface heteroepitaxy process. These epitaxial growth developments should enable improved homojunction and heterojunction silicon carbide prototype devices.

Neudeck, Philip G.↗
NASA NTRS2013

Packaging Technologies for 500C SiC Electronics and Sensors

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Chen, Liang-Yu↗
DOE OSTI2023

High Performance Pd/4H-SiC Epitaxial Schottky Barrier Radiation Detectors for Harsh Environment Applications

Although many refractory metals have been investigated as the choice of contact metal in 4H-SiC devices, palladium (Pd) as a Schottky barrier contact for 4H-SiC radiation detectors for harsh environment applications has not been investigated adequately. Pd is a refractory metal with high material weight-to-thickness ratio and a work function as high as nickel, one of the conventional metal contacts for high performing 4H-SiC Schottky barrier detectors (SBDs). In this article, Pd/4H-SiC epitaxial SBDs have been demonstrated for the first time as a superior self-biased (0 V applied bias) radiation detector when compared to benchmark Ni/4H-SiC SBDs. The Pd/4H-SiC SBD radiation detectors showed a very high energy resolution of 1.9% and 0.49% under self- and optimized bias, respectively, for 5486 keV alpha particles. The SBDs demonstrated a built-in voltage (V bi ) of 2.03 V and a hole diffusion length (L d ) of 30.8 µm. Such high V bi and L d led to an excellent charge collection efficiency of 76% in the self-biased mode. Capacitance mode deep level transient spectroscopy (DLTS) results revealed that the “lifetime-killer” Z 1/2 trap centers were present in the 4H-SiC epilayer. Another deep level trap was located at 1.09 eV below the conduction band minimum and resembles the EH5 trap with a concentration of 1.98 × 10 11 cm –3 and capture cross-section 1.7 × 10 –17 cm –2 ; however, the detector performance was found to be limited by charge trapping in the Z 1/2 center. The results presented in this article revealed the unexplored potential of a wide bandgap semiconductor, SiC, as high-efficiency self-biased radiation detectors. Such high performance self-biased radiation detectors are poised to address the longstanding problem of designing self-powered sensor devices for harsh environment applications e.g., advanced nuclear reactors and deep space missions.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2015

Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range

Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Transistor Gate Drive↗
DOE OSTI2026

World’s First Vertical GaN based High Power (200 kW) Multi-level Traction Electric Drive Design

Vertical GaN (vGaN) technology leverages a fully conductive 3D semiconductor structure, enabling superior power density compared to GaN-on-Si and other wide bandgap devices. It offers a pathway to surpass cost and efficiency limitations of Si and SiC devices in traction applications. However, scaling for high-voltage, high-power systems remains challenging. This paper presents the design of an 800V, 200kW traction inverter utilizing vertical GaN devices. The inverter achieves ultra-high efficiency (> 99.5%) through advanced power module integration and employs multilevel neutral-point-less X-type (NPL.X) inverter topology to ensure optimal traction drive system performance. These innovations demonstrate the potential of vGaN for next￾generation electric propulsion systems.

Alam, Khorshed [General Motors LLC, Detroit, MI (U↗
NASA NTRS2004

Silicon Carbide Diodes Performance Characterization at High Temperatures

NASA Glenn Research center's Electrical Systems Development branch is working to demonstrate and test the advantages of Silicon Carbide (SiC) devices in actual power electronics applications. The first step in this pursuit is to obtain commercially available SiC Schottky diodes and to individually test them under both static and dynamic conditions, and then compare them with current state of the art silicon Schottky and ultra fast p-n diodes of similar voltage and current ratings. This presentation covers the results of electrical tests performed at NASA Glenn. Steady state forward and reverse current-volt (I-V) curves were generated for each device to compare performance and to measure their forward voltage drop at rated current, as well as the reverse leakage current at rated voltage. In addition, the devices were individually connected as freewheeling diodes in a Buck (step down) DC to DC converter to test their reverse recovery characteristics and compare their transient performance in a typical converter application. Both static and transient characterization tests were performed at temperatures ranging from 25 C to 300 C, in order to test and demonstrate the advantages of SiC over Silicon at high temperatures.

Lebron-Velilla, Ramon C.↗
NASA NTRS2002

Glennan Microsystems Initiative

During the 2001-2002 award period, we performed research on Pt/Ti/bare 6H-SiC and bare 4H-SiC interfaces in order to identify their electronic properties as a function of surface preparation. The overall aim of this work is to optimize the electronic properties of metal contacts to SiC as well as the active SiC material itself as a function of surface preparation and subsequent processing. Initially, this work has involved identifying bare surface, subsurface, and metal induced gap states at the metal-SiC contact and correlating energies and densities of deep levels with Schottky barrier heights. We used low energy electron-excited nanoluminescence (LEEN) spectroscopy, X-ray photoemission spectroscopy (XPS), and Secondary Ion Mass Spectrometry (SIMS) in order to correlate electronic states and energy bands with chemical composition, bonding, and crystal structure. A major development has been the discovery of polytype transformations that occur in 4H-SiC under standard microelectronic process conditions used to fabricate SiC devices. Our results are consistent with the stacking fault generation, defect formation, and consequent degradation of SiC recently reported for state-of-the-art ABB commercial diodes under localized electrical stress. Our results highlight the importance of -optimizing process conditions and material properties - anneal times, temperatures and doping to control such structural changes within epitaxial SiC layers. Thus far, we have established threshold times and temperatures beyond which 4H-SiC exhibits 3C-SiC transformation bands for a subset of dopant concentrations and process conditions. On the basis of this temperature time behavior, we have been able to establish an activation energy of approximately 2.5 eV for polytype transformation and dislocation motion. Work continues to establish the fundamental mechanisms underlying the polytype changes and its dependence on material parameters.

Brillson, Leonard J.↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗