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In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
Reproducible bipolar resistive switching characteristics are demonstrated in entire nitride AlN/n-GaN metal-insulator-semiconductor devices. The mechanism involved confirms to trap-controlled space charge limited current theory and can be attributed to the nitrogen vacancies of AlN serving as electron traps that form/rupture electron transport channel by trapping/detrapping electrons. This study will lead to the development of in-situ growth of group-III nitrides by metal-organic chemical vapor deposition as a candidate for next-generation nonvolatile memory device. Moreover, it will be benefit to structure monolithic integrated one-transistor-one-resistor memory with nitride high electron mobility transistors.
The origin of the anomalous frequency dispersion in accumulation capacitance of metal-insulator-semiconductor devices on InGaAs and InP substrates is investigated using modeling, electrical characterization, and chemical characterization. A comparison of the border trap model and the disorder induced gap state model for frequency dispersion is performed. The fitting of both models to experimental data indicate that the defects responsible for the measured dispersion are within approximately 0.8 nm of the surface of the crystalline semiconductor. The correlation between the spectroscopically detected bonding states at the dielectric/III-V interface, the interfacial defect density determined using capacitance-voltage, and modeled capacitance-voltage response strongly suggests that these defects are associated with the disruption of the III-V atomic bonding and not border traps associated with bonding defects within the high-k dielectric.
This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.
The present disclosure relates to resistive field structures that provide improved electric field profiles when used with a semiconductor device. In particular, the resistive field structures provide a uniform electric field profile, thereby enhancing breakdown voltage and improving reliability. In example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage. In another example, the structure is a resistive field plate. Using these resistive field structures, the characteristics of the electric field profile can be independently modulated from the physical parameters of the semiconductor device. Additional methods and architectures are described herein.
The present invention provides methods for etching semiconductor devices, such aluminum nitride resonators. The methods herein allow for devices having improved etch profiles, such that nearly vertical sidewalls can be obtained. In some examples, the method employs a dry etch step with a primary etchant gas that omits BCl.sub.3, a common additive.
Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.
Single Event Effects are a very significant failure mode in modern semiconductor devices that may limit their reliability. Accelerated testing is important for semiconductor industry. Considerable more work is needed in this field to mitigate the problem. Mitigation of this problem will probably come from Physicists and Electrical Engineers working together
In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}), which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.
Two-dimensional (2D) perovskites have gained much attention lately owing to their excellent optoelectronic properties, chemical tunability, and environmental stability. Multiple methods have been devised to synthesize high quality 2D perovskite single crystals, and recent progress in fabricating its heterostructures is notable as well. In particular, with growing interest in 2D van der Waals heterostructures, 2D perovskites have become a strong candidate as a new building block for heterostructures to reveal unique physical properties across different interfaces. Until now, various heterostructure devices of 2D perovskite single crystals with other types of 2D materials such as transition metal dichalcogenides (TMDs) and graphene have been studied, which have shown intriguing results including interlayer excitons and enhanced electronic properties. Here, we introduce various synthetic approaches to realize 2D perovskite single crystals and unique characteristics of their single crystal heterostructures fabricated with precision, possessing sharp interfaces. Moreover, recent studies of semiconductor devices based on 2D perovskite single crystal heterostructures are discussed in-depth. New perspectives to further the horizon in the field of 2D perovskite heterostructures are suggested in this work including the consideration of metal–2D material van der Waals contact, application of dry transfer techniques, electric bias driven ion diffusion studies, and nanocrystal array fabrication. 2D perovskite heterostructure single crystal devices factoring in these novel perspectives will further uncover the true potential of these materials for highly efficient and stable semiconductor devices.
Single Event Effects are a very significant failure mode in modern semiconductor devices that may limit their reliability. Accelerated testing is important for semiconductor industry, so considerably more work is needed in this field to mitigate the problem. Mitigation of this problem will probably come from Nuclear Scientists and Electrical Engineers working together.
A classical method used to characterize the strain in modern semiconductor devices is nanobeam diffraction (NBD) in the transmission electron microscope. One challenge for this method lies in the fact that the smaller the beam becomes, the more difficult it becomes to analyze the resulting diffraction spot pattern. We show that a carefully designed fitting algorithm enables us to reduce the sampling area for the diffraction patterns on the camera chip dramatically (∼1/16) compared to traditional settings without significant loss of precision. The resulting lower magnification of the spot pattern permits the presence of an annular dark field detector, which in turn makes the recording of images for drift correction during NBD acquisition possible. Thus, the reduced sampling size allows acquisition of drift corrected NBD 2D strain maps of up to 3000 pixels while maintaining a precision of better than 0.07%. As an example, we show NBD strain maps of a modern field effect transistor (FET) device. A special filtering feature used in the analysis makes it is possible to measure strain in silicon devices even in the presence of other crystalline materials covering the probed area, which is important for the characterization of the next generation of devices (Fin-FETs).
The paper describes the reasons for the greater difficulty in the passivation of interface defects of III–V semiconductors like GaAs. These include the more complex reconstructions of the starting surface which already possess defect configurations, the possibility of injecting As antisites into the substrate which give rise to gap states, and the need to avoid As-As bonds and As dangling bonds which give rise to gap states. The nature of likely defect configurations in terms of their electronic structure is described. The benefits of diffusion barriers and surface nitridation are discussed.
A new three-level isolated ac-dc power factor correction (PFC) topology with a minimum number of semiconductor devices is the focus of this paper. This topology provides a high input power factor (PF), soft-switching, and higher efficiency than existing isolated ac-dc converters. Furthermore, the proposed circuit has lower voltage rating requirements for the secondary side devices, which leads to a lower total cost and minimizes total converter losses. This article presents a theoretical analysis describing the complete characterization of this new topology, and experimental results on a 1-kW prototype showing high PF and efficiency throughout the operating range.
Nowotny-Juza compounds continue to be explored as candidates for solid-state neutron detectors. Such a device would have greater efficiency, in a compact form, than present day gas-filled 3 He and 10 BF 3 detectors. The 6 Li(n,t) 4 He reaction yields a total Q-value of 4.78 MeV, larger than 10 B, an energy easily identified above background radiations. Hence, devices fabricated from semiconductor compounds having either natural Li (nominally 7.5% 6 Li) or enriched 6 Li (usually 95% 6 Li) as constituent atoms may provide a material for compact high efficiency neutron detectors. Starting material was synthesized by preparing equimolar portions of Li, Zn, and As sealed under vacuum (10 -6 Torr) in quartz ampoules lined with boron nitride and subsequently reacted in a compounding furnace [1]. The raw synthesized material indicated the presence high impurity levels (material and electrical property characterizations). A static vacuum sublimation in quartz was performed to help purify the synthesized material [2], [3]. Bulk crystalline samples were grown from the purified material [4], [5]. Samples were cut using a diamond wire saw, and processed into devices. Bulk resistivity was determined from I–V curve measurements, ranging from 10 6 –10 11 Ω cm. Devices were characterized for sensitivity to 5.48 MeV alpha particles, 337 nm laser light, and neutron sensitivity in a thermal neutron diffracted beam at the Kansas State University TRIGA Mark II nuclear reactor. Thermal neutron reaction product charge induction was measured with a LiZnP device, and the reaction product spectral response was observed.
The local electric field (the field that distorts, polarizes, and weakens polar molecular bonds in dielectrics) has been investigated for hyper-thin dielectrics. Hyper-thin dielectrics are currently required for advanced semiconductor devices. In the work presented, it is shown that the common practice of using a Lorentz factor of L = 1/3, to describe the local electric field in a dielectric layer, remains valid for hyper-thin dielectrics. However, at the very edge of device structures, a rise in the macroscopic/Maxwell electric field E{sub diel} occurs and this causes a sharp rise in the effective Lorentz factor L{sub eff}. At capacitor and transistor edges, L{sub eff} is found to increase to a value 2/3 < L{sub eff} < 1. The increase in L{sub eff} results in a local electric field, at device edge, that is 50%–100% greater than in the bulk of the dielectric. This increase in local electric field serves to weaken polar bonds thus making them more susceptible to breakage by standard Boltzmann and/or current-driven processes. This has important time-dependent dielectric breakdown (TDDB) implications for all electronic devices utilizing polar materials, including GaN devices that suffer from device-edge TDDB.
We demonstrate the ability of a relatively new analytical technique, near-zero-field magnetoresistance (NZFMR), to track atomic-scale phenomena involved in the high-field stressing damage of fully processed Si metal-oxide-semiconductor field-effect transistors. We show that the technique is sensitive to both the Pb0 and Pb1 dangling bond centers and that the presence of both centers can be inferred through NZFMR via hyperfine interactions with the central 29Si atoms of the dangling bonds. The NZFMR results also provide evidence for the redistribution of mobile hydrogen atoms at the Si/SiO2 interface and also a potential change in the average dipolar coupling constant between electrons in neighboring defects. This work shows that NZFMR offers significant analytical power for studying technologically relevant semiconductor device reliability problems and has advantages in experimental simplicity over comparable techniques.
Time-domain current measurements are widely used to characterize semiconductor material properties, such as carrier mobility, doping concentration, carrier lifetime, and the static dielectric constant. It is therefore critical that these measurements be theoretically understood if they are to be successfully applied to assess the properties of materials and devices. In this paper, we derive generalized relations for describing current-density transients in planar semiconductor devices at uniform temperature. By spatially averaging the charge densities inside the semiconductor, we are able to provide a rigorous, straightforward, and experimentally relevant way to interpret these measurements. The formalism details several subtle aspects of current transients, including how the electrode charge relates to applied bias and internal space charge, how the displacement current can alter the apparent free-carrier current, and how to understand the integral of a charge-extraction transient. We also demonstrate how the formalism can be employed to derive the current transients arising from simple physical models, like those used to describe charge extraction by linearly increasing voltage (CELIV) and time-of-flight experiments. In doing so, we find that there is a nonintuitive factor-of-2 reduction in the apparent free-carrier concentration that can be easily missed, for example, in the application of charge-extraction models. Finally, to validate our theory and better understand the different current contributions, we perform a full time-domain drift-diffusion simulation of a CELIV trace and compare the results to our formalism. As expected, our analytic equations match precisely with the numerical solutions to the drift-diffusion, Poisson, and continuity equations. Furthermore, overall, our formalism provides a straightforward and general way to think about how the internal space-charge distribution, the electrode charge, and the externally applied bias translate into a measured current transient in a planar semiconductor device.