Modeling and Mitigation of Multi-Loops Related Device Overvoltage in Three Level Active Neutral Point Clamped Converter
This paper establishes an analytical model for the device drain-source overvoltage related to the two loops in three level active neutral point clamped (3L-ANPC) converters. Taking into account the non-linear device output capacitance, two commonly used modulations are investigated in detail. The result shows that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the non-active clamping switch off, the effect of the non-linear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in PCB and busbar design. A 500 kVA 3L-ANPC converter using SiC MOSFETs is built and tested. The experimental results validate the overvoltage model of the two modulations as well as the busbar design. With the non-active clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.