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All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Simplified Correction Of Errors In Reed-Solomon Codes

New decoder realized by simplified pipeline architecture. Simplified procedure for correction of errors and erasures in Reed-Solomon codes expected to result in simpler decoding equipment. Development widens commercial applicability of Reed-Solomon codes, used to correct bursts of errors in digital communication and recording systems. Improved decoder less complex. Made more regular, simple, and suitable for implementation in both VLSI and software.

Truong, T. K.↗
NASA NTRS1980

Synchronization of Reed-Solomon codes

The synchronization capabilities of Reed-Solomon codes when an appropriate coset of the code is used instead of the code itself are examined. In this case an E-error correcting Reed-Solomon code is transformed into a code capable of determining that there are m symbols out of sync, if e symbol errors occurred, whenever m + e E. In the event that m = 0, i.e., the word is in sync, then decoder will correct any pattern of E - 1 on fewer symbol errors.

Miller, R. L.↗
NASA NTRS1981

An experimental study of the concatenated Reed-Solomon/Viterbi channel coding system performance and its impact on space communications

The need for efficient space communication at very low bit error probabilities to the specification and implementation of a concatenated coding system using an interleaved Reed-Solomon code as the outer code and a Viterbi-decoded convolutional code as the inner code. Experimental results of this channel coding system are presented under an emulated S-band uplink and X-band downlink two-way space communication channel, where both uplink and downlink have strong carrier power. This work was performed under the NASA End-to-End Data Systems program at JPL. Test results verify that at a bit error probability of 10 to the -6 power or less, this concatenated coding system does provide a coding gain of 2.5 dB or more over the Viterbi-decoded convolutional-only coding system. These tests also show that a desirable interleaving depth for the Reed-Solomon outer code is 8 or more. The impact of this "virtually" error-free space communication link on the transmission of images is discussed and examples of simulation results are given.

Liu, K. Y.↗
NASA NTRS1983

VLSI Reed-Solomon Encoder

Modular Reed-solomon encoder uses identical custom VLSI chips called "symbol slices." By cascading and properly interconnecting group of these chips, encoder is made for any desired error-correcting capability and interleaving level. VLSI encoder requires only one-tenth the number of chips required by conventional Reed-Solomon Circuit implemented with discrete IC's.

Liu, K. Y.↗
NASA NTRS1981

Reeds computer code

The REEDS (rocket exhaust effluent diffusion single layer) computer code is used for the estimation of certain rocket exhaust effluent concentrations and dosages and their distributions near the Earth's surface following a rocket launch event. Output from REEDS is used in producing near real time air quality and environmental assessments of the effects of certain potentially harmful effluents, namely HCl, Al2O3, CO, and NO.

Bjork, C.↗
NASA NTRS1981

Conceptual design for a universal Reed-Solomon decoder

An algorithm which enables one Reed-Solomon decoder to process other Reed-Solomon encoded data from a different code is presented. The sole requirement is that both codes have the same length, the same rate, and the same field of coefficients. It is pointed out that only very simple pre- and post-processing hardware is needed to resolve an encoder/decoder incompatibility and that no encoder modification is needed.

Miller, R. L.↗
NASA NTRS1985

On the binary weight distribution of some Reed-Solomon codes

Consider an (n,k) linear code with symbols from GF(2 sup M). If each code symbol is represented by a m-tuple over GF(2) using certain basis for GF(2 sup M), a binary (nm,km) linear code is obtained. The weight distribution of a binary linear code obtained in this manner is investigated. Weight enumerators for binary linear codes obtained from Reed-Solomon codes over GF(2 sup M) generated by polynomials, (X-alpha), (X-l)(X-alpha), (X-alpha)(X-alpha squared) and (X-l)(X-alpha)(X-alpha squared) and their extended codes are presented, where alpha is a primitive element of GF(2 sup M). Binary codes derived from Reed-Solomon codes are often used for correcting multiple bursts of errors.

Lin, S.↗
NASA NTRS1985

Reed-solomon Code Synchronization Revisited

A concatenated coding consisting of an inner (7, 1/2) convolutional code and an outer (255, 223) Reed-Solomon code was recommended by the Consultative Committee for Space Data Systems for cross-supported space missions. The Reed-Solomon code that was chosen makes use of the Berlekamp encoding algorithm. Some peculiarities of this code that could give rise to synchronization problems are examined. Suggestions are given to alleviate these problems.

Deutsch, L. J.↗
NASA NTRS1987

The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

Hsu, I. S.↗
NASA NTRS1987

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗
NASA NTRS1988

The decoding of Reed-Solomon codes

Reed-Solomon (RS) codes form an important part of the high-rate downlink telemetry system for the Magellan mission, and the RS decoding function for this project will be done by DSN. Although the basic idea behind all Reed-Solomon decoding algorithms was developed by Berlekamp in 1968, there are dozens of variants of Berlekamp's algorithm in current use. An attempt to restore order is made by presenting a mathematical theory which explains the working of almost all known RS decoding algorithms. The key innovation that makes this possible is the unified approach to the solution of the key equation, which simultaneously describes the Berlekamp, Berlekamp-Massey, Euclid, and continued fractions approaches. Additionally, a detailed analysis is made of what can happen to a generic RS decoding algorithm when the number of errors and erasures exceeds the code's designed correction capability, and it is shown that while most published algorithms do not detect as many of these error-erasure patterns as possible, by making a small change in the algorithms, this problem can be overcome.

Mceliece, R. J.↗
NASA NTRS1990

Tutorial on Reed-Solomon error correction coding

This tutorial attempts to provide a frank, step-by-step approach to Reed-Solomon (RS) error correction coding. RS encoding and RS decoding both with and without erasing code symbols are emphasized. There is no need to present rigorous proofs and extreme mathematical detail. Rather, the simple concepts of groups and fields, specifically Galois fields, are presented with a minimum of complexity. Before RS codes are presented, other block codes are presented as a technical introduction into coding. A primitive (15, 9) RS coding example is then completely developed from start to finish, demonstrating the encoding and decoding calculations and a derivation of the famous error-locator polynomial. The objective is to present practical information about Reed-Solomon coding in a manner such that it can be easily understood.

Geisel, William A.↗
NASA NTRS1992

Control Circuit For Reed-Solomon Encoder

Control circuit designed for use with commercially available AHA4610 Reed-Solomon encoder. Needed to select depth of interleaving and to synchronize input and output blocks of data and parity bits with suitable clock signals. Circuit provides synchronizing and control signals for Reed-Solomon encoder. Encoder can operate with asynchronous input and output data streams at rates up to 80 Mb/s. Interleaving depth selectable, and accommodation to input data rate automatic.

Ross, Douglas↗
NASA NTRS1992

Tangential-Entry Injector With Internal Reed Valve

Liquid-spray-injecting device provides designed pressure drop versus rate of flow to help meter flow. Includes cylinder with tangential entry slots and internal reed valve. Tangential entry imparts swirling motion to liquid, resulting in finely atomized liquid spray. Reeds vary flow areas of entry slots by deflecting in response to pressure of liquid. Variation alters pressure-versus-flow characteristic. Device used to provide wide range of throttleability for liquid fuel injected into combustion chamber or engine.

Cox, George B., Jr.↗
NASA NTRS1990

A burst-correcting algorithm for Reed Solomon codes

The Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful error-correcting cyclic codes. Among the non-binary BCH codes, the most important subclass is the Reed Solomon (RS) codes. Reed Solomon codes have the ability to correct random and burst errors. It is well known that an (n,k) RS code can correct up to (n-k)/2 random errors. When burst errors are involved, the error correcting ability of the RS code can be increased beyond (n-k)/2. It has previously been show that RS codes can reliably correct burst errors of length greater than (n-k)/2. In this paper, a new decoding algorithm is given which can also correct a burst error of length greater than (n-k)/2.

Chen, J.↗
NASA NTRS1994

Trace-shortened Reed-Solomon codes

Reed-Solomon (RS) codes have been part of standard NASA telecommunications systems for many years. RS codes are character-oriented error-correcting codes, and their principal use in space applications has been as outer codes in concatenated coding systems. However, for a given character size, say m bits, RS codes are limited to a length of, at most, 2(exp m). It is known in theory that longer character-oriented codes would be superior to RS codes in concatenation applications, but until recently no practical class of 'long' character-oriented codes had been discovered. In 1992, however, Solomon discovered an extensive class of such codes, which are now called trace-shortened Reed-Solomon (TSRS) codes. In this article, we will continue the study of TSRS codes. Our main result is a formula for the dimension of any TSRS code, as a function of its error-correcting power. Using this formula, we will give several examples of TSRS codes, some of which look very promising as candidate outer codes in high-performance coded telecommunications systems.

Mceliece, R. J.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗