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At least 37 records · Page 2

Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR susceptibility is explored. SEGR evaluation of gamma-irradiated power MOSFETs suggests a non-significant SEGR susceptibility enhancement due to accumulated dose from gamma rays. During SEGR testing, an unexpected enhanced dose effect from heavy-ion irradiation was detected. We demonstrate that this effect could be due to direct ionization by two or more ions at the same channel location. The probability on-orbit for such an occurrence is near-zero given the low heavy-ion fluence over a typical mission lifetime, and did not affect SEGR susceptibility. The results of this work can be used to bound the risk of SEGR in power MOSFETs considered for insertion into spacecraft and instruments.

Lauenstein, Jean-Marie

Towards Accelerated Aging Methodologies and Health Management of Power MOSFETs (Technical Brief)

Understanding aging mechanisms of electronic components is of extreme importance in the aerospace domain where they are part of numerous critical subsystems including avionics. In particular, power MOSFETs are of special interest as they are involved in high voltage switching circuits such as drivers for electrical motors. With increased use of electronics in aircraft control, it becomes more important to understand the degradation of these components in aircraft specific environments. In this paper, we present an accelerated aging methodology for power MOSFETs that subject the devices to indirect thermal overstress during high voltage switching. During this accelerated aging process, two major modes of failure were observed - latch-up and die attach degradation. In this paper we present the details of our aging methodology along with details of experiments and analysis of the results.

Celaya, Jose R.

Automated System Tests High-Power MOSFET's

Computer-controlled system tests metal-oxide/semiconductor field-effect transistors (MOSFET's) at high voltages and currents. Measures seven parameters characterizing performance of MOSFET, with view toward obtaining early indication MOSFET defective. Use of test system prior to installation of power MOSFET in high-power circuit saves time and money.

Huston, Steven W.

Observations of Single Event Failure in Power MOSFETS

The first compendium of single event test data for power MOSFETs provides failure thresholds from burnout or gate rupture for over 100 devices of eight manufacturers. Ordering the data has also provided some useful insights.

bipolar power transistors single event test burnou

Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure

This paper presents research results dealing with power MOSFETs (metal oxide semiconductor field effect transistor) within the prognostics and health management of electronics. Experimental results are presented for the identification of the on-resistance as a precursor to failure of devices with die-attach degradation as a failure mechanism. Devices are aged under power cycling in order to trigger die-attach damage. In situ measurements of key electrical and thermal parameters are collected throughout the aging process and further used for analysis and computation of the on-resistance parameter. Experimental results show that the devices experience die-attach damage and that the on-resistance captures the degradation process in such a way that it could be used for the development of prognostics algorithms (data-driven or physics-based).

Celaya, Jose R.

Recent Power MOSFET Test Results

The results of recent Single Event Effect (SEE) testing of newly available power MOSFETS are presented.

radiation hard power solutions

Interpreting Space-Mission LET Requirements for SEGR in Power MOSFETs

Single-event gate rupture (SEGR) is a potentially catastrophic failure mechanism of power MOSFETs biased in the off-state. In part due to the severity of-SEGR consequences and in part due to the difficulty of accurated SEGR rate estimation, SEGR mitigation me1hodologies emphasize risk avoidance, using heavy-ion accelerator testing to define safe operating conditions for a surface-incident linear energy transfer {LET). This "safe-operating area" (SOA) within which the device may be biased without experiencing SEGR is then often derated by a prescribed factor to ensure low risk of SEGR. Although research in 1996 indicated that such LET-based SEGR hardness requiremen1s could provide false assurance of safe operation unless one also considered· ion energy], most mission SEGR requirements are still specified in terms of surface-incident LET. Moreover, terrestrial SEGR tests at a given surface-incident LET are limited by the small number of ion species and energies available at heavy-ion accelerators. In comparison, the on-orbit radiation environment is composed of all of the naturally-occurring elements with peak fluxes at nearly GeV/nucleon energies. The primary objective of this study is to examine whether typical derating of high-energy heavy-ion accelerator test data bounds the risk for SEGR from higher-energy on-orbit ions with the mission LET requirement.

Lauenstein, Jean-Marie

Single-Event Gate Rupture and Single-Event Burnout Test Results Performed on Hi-Rel Fuji Power MOSFETs: 2SK4217, 2SK4152, 2SK4155, and 2SK4158

Several newly available Hi-Rel total dose hardened power MOSFETs manufactured by Fuji Electric Device Technology Co. Ltd (FDT) in conjunction with the Japan Aerospace Exploration Agency (JAXA) were tested for single-event gate rupture (SEGR) and single-event burnout (SEB). The safe-operating area (SOA) of the 2SK4217 (a 100 V rated device), 2SK4152 (130 V), 2SK4155 (200 V), and the 2SK4158 (250 V) were tested with silver (Ag) and xenon (Xe) ions having incident LETs of 42.2 and 53.1 MeV cm2/mg, respectively. Test results show these devices are comparable to currently available total dose hardened technology.

Selva, Luis E.

Investigations into the Power MOSFET SEGR Phenomenon and its Physical Mechanism

The state of understanding of the destructive SEGR event in power MOSFETs is relatively mature with large published efforts, both experimental and theoretical. However, gasps remain in the uderstanding of the phenomenon, including unexplained anomalies, emperical-only dependencies on some important device and incident ion physical parameters, and limited insight into latent effets.

MOSFET SEGR

Single-Event Latchup Testing of the Micrel MIC4424 Dual Power MOSFET Driver

We conducted 47 exposures of four different MIC4424 devices and did not observe any SEL or high-current events. This included worst-case conditions with a LET of 81 MeV-sq cm/mg, applied voltage of 18.5 V, a case temperature greater than 120 C, and a final fluence of 1x10(exp 7)/sq cm. We also monitored both the outputs for the presence of SETs. While the period of the 1 MHz square wave was slightly altered in some cases, no pulses were added or deleted. 1. Purpose: The purpose of this testing is to characterize the BiCMOS/DMOS Micrel MIC4424 dual, non-inverting MOSFET driver for single-event latchup (SEL) susceptibility. These data will be used for flight lot evaluation purposes. 2. Devices Tested: The MIC4423/4424/4425 family are highly reliable BiCMOS/DMOS buffer/driver MOSFET drivers. They are higher output current versions of the MIC4426/4427/4428. They can survive up to 5V of noise spiking, of either polarity, on the ground pin. They can accept, without either damage or logic upset, up to half an amp of reverse current (either polarity) forced back into their outputs. Primarily intended for driving power MOSFETs, the MIC4423/4424/4425 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak currents, and fast switching times. Heavily loaded clock lines, coaxial cables, or piezoelectric transducers are some examples. The only known limitation on loading is that total power dissipated in the driver must be kept within the maximum power dissipation limits of the package. Five (5) parts were provided for SEL testing. We prepared four parts for irradiation and reserved one piece as an un-irradiated control. More information about the devices can be found in Table 1. The parts were prepared for testing by removing the lid from the CDIP package to expose the target die. The parts were then soldered to small copper circuit adapter boards for easy handling. These parts are fabricated in a bulk BiCMOS/DMOS technology. Since we do not know the number of overlayers used in the fabrication processes, linear energy transfer calculations are determined based on the top-surface incident ion species and kinetic energy.

Power MOSFET

Single-Event Effect Testing of the Vishay Si7414DN n-Type TrenchFET(Registered Trademark) Power MOSFET

This study was being undertaken to determine the single event effect susceptibility of the commercial Vishay 60-V TrenchFET power MOSFET. Heavy-ion testing was conducted at the Texas AM University Cyclotron Single Event Effects Test Facility (TAMU) and the Lawrence Berkeley National Laboratory BASE Cyclotron Facility (LBNL). In addition, initial 200-MeV proton testing was conducted at Massachusetts General Hospital (MGH) Francis H. Burr Proton Beam Therapy Center. Testing was performed to evaluate this device for single-event effects from lower-LET, lighter ions relevant to higher risk tolerant space missions.

proton testing

Single Event Effect Testing of the SSDI SFF6661 N-Channel Power MOSFET

This irradiation campaign was performed to evaluate the destructive single event effect (SEE) susceptibility of a n-channel power MOSFET from SSDI for space-based instrumentation. Testing was performed at Michigan State University’s (MSU) Facility for Rate Isotope Beams (FRIB) using an LET of 50.5 MeV·cm 2 /mg

Landen D. Ryder

Paralleling power MOSFETs in their active region: Extended range of passively forced current sharing

A simple passive circuit that improves current balance in parallelled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive are exhibited. A nonlinear circuit consisting of diodes and resistors generates the differential gate potential required to correct for unbalance while maintaining low losses over a range of current. Also application of a thin tape wound magnetic core to effect dynamic current balance is reviewed, and a simple theory is presented showing that for operation in the active region the branch currents tend to revert to their normal unbalanced values even if the core is not driven into saturation. Results of several comparative experiments are given.

Niedra, Janis M.

Testing guideline for single event gate rupture (SEGR) of power MOSFETs

The purpose of this document is two-fold. First, the document lists and discusses many of the issues important to understand when testing power MOSFETs. Second, the recommended approach for using radiation test data to define the device application requirements is presented. These include SEE rate calculation, data analysis, and derating guidelines. A significant amount of work has been done on the basic effects of SEB and SEGR. References are supplied where seminal work has been done on the topic at hand. The reader is urged to review the references if the testing issues or mission application at hand are complex.

Scheick, Leif