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Single-event gate rupture (SEGR)in vertical power MOSFETs is induced by charge deposited in the epitaxial region (below the gate oxide) in concert with the weakening of the oxide, both are a result of the ion passage.
A several-kilowatt power level, fast-variable linear resistor has been synthesized by using analog components to control the conductance of power MOSFETs. Risetimes observed have been as short as 500 ns with respect to the control signal and 1 to 2 microsec with respect to the power source voltage. A variant configuration of this load that dissipates a constant power set by a control signal is indicated. Replacement of the MOSFETs by static induction transistors to increase power handling, speed, and radiation hardness is discussed.
A several kilowatt power level, fast-variable linear resistor was synthesized by using analog components to control the conductance of power MOSFETs. Risetimes observed have been as short as 500 ns with respect to the control signal and 1 to 2 microseconds with respect to the power source voltage. A variant configuration of this load that dissipates a constant power set by a control signal is indicated. Replacement of the MOSFETs by static induction transistors (SITs) to increase power handling, speed and radiation hardness is discussed.
This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.
The low temperature operation of a 48 W, 50 kHz, 36/12 V pulse width modulated (PWM) buck de-de power converter designed with standard commercially available components and devices is reported. The efficiency of the converter increased from 85.6% at room temperature (300 K) to 92.0% at liquid nitrogen temperature (77 K). The variation of power MOSFET, diode rectifier, and output filter inductor loss with temperature is discussed. Relevant current, voltage. and power waveforms are also included.
The initial design and evaluation of a 5 kW arcjet power electronics breadboard which as been integrated with a modified 1 kW design laboratory arcjet is presented. A single stage, 5 kW full bridge, pulse width modulated (PWM), power converter was developed which was phase shift regulated. The converter used metal oxide semiconductor field effect transistor (MOSFET) power switches and incorporated current mode control and an integral arcjet pulse ignition circuit. The unoptimized power efficiency was 93.5 and 93.9 percent at 5 kW and 50A output at input voltages of 130 and 150V, respectively. Line and load current regulation at 50A output was within one percent. The converter provided up to 6.6 kW to the arcjet with simulated ammonia used as a propellant.
The initial design and evaluation of a 5 kW arcjet power electronics breadboard which as been integrated with a modified 1 kW design laboratory arcjet is presented. A single stage, 5 kW full bridge, pulse width modulated (PWM), power converter was developed which was phase shift regulated. The converter used metal oxide semiconductor field effect transistor (MOSFET) power switches and incorporated current mode control and an integral arcjet pulse ignition circuit. The unoptimized power efficiency was 93.5 and 93.9 percent at 5 kW and 50A output at input voltages of 130 and 150V, respectively. Line and load current regulation at 50A output was within one percent. The converter provided up to 6.6 kW to the arcjet with simulated ammonia used as a propellant.
Simple circuit makes currents more nearly equal. Addition of diodes and adjustable-tap resistor increases operating range over which drain currents in two unmatched power MOSFET's brought more nearly into balance.
Low-temperature (77 K) operation of a 42/28 V, 175 W, 50 kHz PWM Buck DC/DC converter designed with commercially available components is reported. Overall, the converter losses decreased at 77 K compared to room temperature operation. A full-load efficiency of 97 percent was recorded at liquid-nitrogen temperature, compared to 95.8 percent at room temperature. Power MOSFET operation improved significantly where as the output rectifier operation deteriorated at low-temperature. The performance of the output filter inductor and capacitor did not change significantly at 77 K compared to room temperature performance. It is possible to achieve high-density and high efficiency power conversion at low-temperatures due to improved electronic, electrical and thermal properties of materials.
The NASA Langley 6 inch magnetic suspension and balance system (MSBS) requires an independently controlled bidirectional DC power source for each of six positioning electromagnets. These electromagnets provide five-degree-of-freedom control over a suspended aerodynamic test model. Existing power equipment, which employs resistance coupled thyratron controlled rectifiers as well as AC to DC motor generator converters, is obsolete, inefficient, and unreliable. A replacement six phase bidirectional controlled bridge rectifier is proposed, which employs power MOSFET switches sequenced by hybrid analog/digital circuits. Full load efficiency is 80 percent compared to 25 percent for the resistance coupled thyratron system. Current feedback provides high control linearity, adjustable current limiting, and current overload protection. A quenching circuit suppresses inductive voltage impulses. It is shown that 20 kHz interference from positioning magnet power into MSBS electromagnetic model position sensors results predominantly from capacitively coupled electric fields. Hence, proper shielding and grounding techniques are necessary. Inductively coupled magnetic interference is negligible.
The NASA Langley 6-inch Magnetic Suspension and Balance System (6-in. MSBS) requires an independently controlled bidirectional dc power source for each of six positioning electromagnets. These electromagnets provide five-degree-of-freedom control over a suspended aerodynamic test model. Existing power equipment, which employs resistance-coupled thyratron-controlled rectifiers as well as ac to dc motor-generator converters, is obsolete, inefficient, and unreliable. A replacement six-phase bidirectional controlled bridge rectifier is proposed, which employs power MOSFET switches sequenced by hybrid analog/digital circuits. Full-load efficiency is 80 percent compared with 25 percent for the resistance-coupled thyratron system. Current feedback provides high control linearity, adjustable current limiting, and current overload protection. A quenching circuit suppresses inductive voltage impulses. It is shown that 20-kHz interference from positioning magnet power into MSBS electromagnetic model position sensors results predominantly from capacitively coupled electric fields. Hence, proper shielding and grounding techniques are necessary. Inductively coupled magnetic interference is negligible.
We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.
Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching [1- 4] for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications [5-7] to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be realized in experimental SiC devices, primarily due to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems [9]. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high temperature and/or high power SiC electronics are identified.
Electronic load circuit for displaying current/voltage characteristic curves of power sources uses low-cost low-power CMOS operational amplifiers to control load current flowing through power MOSFET Q2 and main load transistor Q3. Thermal cutoff device turns off transistor Q3 in case of overload. To maximize battery life, battery is connected via "push-to-read" momentary-contact pushbutton switch.
Adjustable electronic load in solar-cell-array test instrument uses ten power MOSFET's and eight resistors. Two gate-control voltages adjusting load are derived from single, manually-operated, ganged potentiometer control. Third adjustable resistor adjusts relative turn-on points of two groups of transistors.
A power source was developed to support testing for the Space Station Freedom Power Management and Distribution (PMAD) DC Testbed. The intent was to simulate as closely as possible the steady-state and transient responses of a solar array. Several breadboards and one thermal prototype were built and tested. Responses were successfully verified and improved upon during successive breadboards. The completed 90-string simulator consists of four power MOSFETs, four 25 watt source resistors, and four 250 watt drain source bypass resistors per string, in addition to the control circuitry.
A power source was developed to support testing for the Space Station Freedom Power Management and Distribution (PMAD) DC Testbed. The intent was to simulate as closely as possible the steady-state and transient responses of a solar array. Several breadboards and one thermal prototype were built and tested. Responses were successfully verified and improved upon during successive breadboards. The completed 90-string simulator consists of four power MOSFETs, four 25-watt source resistors, and four 250-watt drain source bypass resistors per string, in addition to the control circuitry.
This application concerns a simple passive circuit that improves current balance in paralleled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive. A nonlinear circuit consisting of diodes and resistors generates a differential gate potential required to correct for unbalance while maintaining low losses over a range of current.