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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2

All sources NASA NTRS DOE OSTI

DOE OSTI2018

Differences in total stem value when merchandizing with a tracked processor versus a knuckle–boom loader in Pinus taeda

Using tracked processors over knuckle–boom loaders to increase total value per tree when merchandizing timber on the landing has become a topic of interest in the southeastern region of the United States. This study compared merchantability values, product classes, and product weights of loblolly pine (Pinus taeda) for both machines to determine if there was a significant difference between machines when processing the same tree. In order to process the same tree twice, the chains from the tracked processor had to be removed from the bottom saw bar. This allowed the processor to simulate the merchandising process without actually marking or cutting the tree for a more realistic comparison. Data were analyzed using paired t–tests and two–way ANOVA models. Results depicted that when diameter and total lengths are visually estimated by the knuckle–boom loader. A significant difference in value occurs, however, once diameter and total length are modified to match the tracked processors for more accurate measurements, no difference in value was seen. Here, these results demonstrate that until mill specifications become more stringent, there is little incentive for loggers to purchase a tracked processor if their only motivation is to increase merchantability values.

42 ENGINEERING↗

DOE OSTI2019

Quantum supremacy using a programmable superconducting processor

The promise of quantum computers is that certain computational tasks might be executed exponentially faster on a quantum processor than on a classical processor. A fundamental challenge is to build a high-fidelity processor capable of running quantum algorithms in an exponentially large computational space. Here we report the use of a processor with programmable superconducting qubits to create quantum states on 53 qubits, corresponding to a computational state-space of dimension 2 53 (about 10 16 ). Measurements from repeated experiments sample the resulting probability distribution, which we verify using classical simulations. Our Sycamore processor takes about 200 seconds to sample one instance of a quantum circuit a million times—our benchmarks currently indicate that the equivalent task for a state-of-the-art classical supercomputer would take approximately 10,000 years. Finally, this dramatic increase in speed compared to all known classical algorithms is an experimental realization of quantum supremacy for this specific computational task, heralding a much-anticipated computing paradigm.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2021

Efficient flexible characterization of quantum processors with nested error models

We present a simple and powerful technique for finding a good error model for a quantum processor. The technique iteratively tests a nested sequence of models against data obtained from the processor, and keeps track of the best-fit model and its wildcard error (a metric of the amount of unmodeled error) at each step. Each best-fit model, along with a quantification of its unmodeled error, constitutes a characterization of the processor. We explain how quantum processor models can be compared with experimental data and to each other. We demonstrate the technique by using it to characterize a simulated noisy two-qubit processor.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2011

Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array.

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable field programmable gate array (FPGA)-based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hard-core processor built into the FPGA or as a soft-core processor built out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA-based soft-core processors for use in future NBA systems: the MicroBlaze (uB), the open-source Leon3, and the licensed Leon3. Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration.

99 GENERAL AND MISCELLANEOUS↗

DOE OSTI2016

Communications systems and methods for subsea processors

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

02 PETROLEUM↗

DOE OSTI2016

Multiple core computer processor with globally-accessible local memories

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Light-weight cache coherence for data processors with limited data sharing

A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Multiple core computer processor with globally-accessible local memories

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Subsea processor for underwater drilling operations

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. The subsea processor may relay information to the surface for recording or monitoring. The subsea processor may also be programmed with a model from which to base operation of the BOP, such as in emergency conditions.

42 ENGINEERING↗

DOE OSTI2018

Algorithmic Patterns for $$\mathcal {H}$$-Matrices on Many-Core Processors

In this work, we consider the reformulation of hierarchical ( $\mathcal {H}$ ) matrix algorithms for many-core processors with a model implementation on graphics processing units (GPUs). $\mathcal {H}$ matrices approximate specific dense matrices, e.g., from discretized integral equations or kernel ridge regression, leading to log-linear time complexity in dense matrix–vector products. The parallelization of $\mathcal {H}$ matrix operations on many-core processors is difficult due to the complex nature of the underlying algorithms. While previous algorithmic advances for many-core hardware focused on accelerating existing $\mathcal {H}$ matrix CPU implementations by many-core processors, we here aim at totally relying on that processor type. As main contribution, we introduce the necessary parallel algorithmic patterns allowing to map the full $\mathcal {H}$ matrix construction and the fast matrix–vector product to many-core hardware. In this work, crucial ingredients are space filling curves, parallel tree traversal and batching of linear algebra operations. The resulting model GPU implementation hmglib is the, to the best of the authors knowledge, first entirely GPU-based Open Source $\mathcal {H}$ matrix library of this kind. We investigate application examples as present in kernel ridge regression, Gaussian Process Regression and kernel-based interpolation. In this context, an in-depth performance analysis and a comparative performance study against a standard multi-core CPU $\mathcal {H}$ matrix library highlights profound speedups of our many-core parallel approach.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Random access quantum information processors using multimode circuit quantum electrodynamics

Qubit connectivity is an important property of a quantum processor, with an ideal processor having random access—the ability of arbitrary qubit pairs to interact directly. This a challenge with superconducting circuits, as state-of-the-art architectures rely on only nearest-neighbor coupling. Here, we implement a random access superconducting quantum information processor, demonstrating universal operations on a nine-qubit memory, with a Josephson junction transmon circuit serving as the central processor. The quantum memory uses the eigenmodes of a linear array of coupled superconducting resonators. We selectively stimulate vacuum Rabi oscillations between the transmon and individual eigenmodes through parametric flux modulation of the transmon frequency. Utilizing these oscillations, we perform a universal set of quantum gates on 38 arbitrary pairs of modes and prepare multimode entangled states, all using only two control lines. We thus achieve hardware-efficient random access multi-qubit control in an architecture compatible with long-lived microwave cavity-based quantum memories.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Mitigating cosmic-ray-like correlated events with a modular quantum processor

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error-correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to, e.g., cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit-energy relaxation times. Here, in this study, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic-ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over 85%), events in separate modules only display approximately 2% correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke errorcorrection codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.

Wu, Xuntao [Univ. of Chicago, IL (United States)] ↗

DOE OSTI2025

Efficient frequency allocation for superconducting quantum processors using improved optimization techniques

Building on previous research on frequency allocation optimization for superconducting circuit quantum processors, this work incorporates several techniques to improve overall solution quality. Here, we introduce constraints and imposed edgewise differences help to improve the optimization results. We also introduce optimization variables for the orientation of each edge, defined as the direction from the control qubit to the target qubit, to be chosen during optimization. To scale up to larger processors, multimodule designs are employed with various boundary conditions, thereby enhancing the collective yield. These enhancements allow for greater flexibility in processor design by eliminating the need for handpicked orientations. We support the efficient assembly of large processors with dense connectivity by choosing the best boundary conditions. Examples demonstrate that, at low computational cost, this optimization approach finds a frequency configuration for a square chip with over 1000 qubits and over 10% yield at much larger dispersion levels than required by previous approaches.

Zhang, Zewen [Argonne National Laboratory (ANL), A↗

DOE OSTI2021

Quantum Computer-Aided Design: Digital Quantum Simulation of Quantum Processors

With the increasing size of quantum processors, submodules that constitute the processor hardware will become too large to accurately simulate on a classical computer. Therefore, one would soon have to fabricate and test each new design primitive and parameter choice in time-consuming coordination between design, fabrication, and experimental validation. Here we show how one can design and test the performance of next-generation quantum hardware—by using existing quantum computers. Focusing on superconducting transmon processors as a prominent hardware platform, we compute the static and dynamic properties of individual and coupled transmons. We show how the energy spectra of transmons can be obtained by variational hybrid quantum-classical algorithms that are well suited for near-term noisy quantum computers. In addition, single- and two-qubit gate simulations are demonstrated via Suzuki-Trotter decomposition. Our methods pave a promising way towards designing candidate quantum processors when the demands of calculating submodule properties exceed the capabilities of classical computing resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Mitigation of Cosmic Rays-Induced Errors in Superconducting Quantum Processors

Environmental radioactivity and cosmic-rays have recently been identified as a source of decoherence in super-conducting quantum bits (qubits). In particular, the absorption of cosmic-ray muons and gamma rays emitted by naturally occurring radioactive isotopes in the qubit substrate leads to correlated errors in superconducting quantum processors, posing significant challenges to quantum error correction. To enable quantum computing to scale, it is therefore necessary the devel-opment of mitigation strategies to prevent, or keep under control, error bursts due to particle impacts in the chip. While most environmental radioactive sources can be effectively suppressed using dedicated shielding, cosmic-ray muons, with their high penetration capability, can only be mitigated by moving the entire facility in a deep underground laboratory. This work explores the potential for developing a novel class of quantum processors equipped with an active veto system to protect superconducting-based quantum computers from the detrimental effects of atmospheric muons. Such a device would enable the identification of an atmospheric muon interaction within the processor and veto all operations performed during the occurrence of such an interaction. By demonstrating high detection efficiency and negligible dead time, we aim to establish that the future of quantum processors can be envisioned in above-around facilities.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2017

Acceleration of the IMplicit–EXplicit nonhydrostatic unified model of the atmosphere on manycore processors

We present the acceleration of an IMplicit-EXplicit (IMEX) nonhydrostatic atmospheric model on manycore processors such as graphic processing units (GPUs) and Intel's Many Integrated Core (MIC) architecture. IMEX time integration methods sidestep the constraint imposed by the Courant-Friedrichs-Lewy condition on explicit methods through corrective implicit solves within each time step. In this work, we implement and evaluate the performance of IMEX on manycore processors relative to explicit methods. Using 3D-IMEX at Courant number C = 15, we obtained a speedup of about 4x relative to an explicit time stepping method run with the maximum allowable C = 1. Moreover, the unconditional stability of IMEX with respect to the fast waves means the speedup can increase significantly with the Courant number as long as the accuracy of the resulting solution is acceptable. We show a speedup of 100x at C = 150 using 1D-IMEX to demonstrate this point. Several improvements on the IMEX procedure were necessary in order to outperform our results with explicit methods: (a) reducing the number of degrees of freedom of the IMEX formulation by forming the Schur complement, (b) formulating a horizontally explicit vertically implicit 1D-IMEX scheme that has a lower workload and better scalability than 3D-IMEX, (c) using high-order polynomial preconditioners to reduce the condition number of the resulting system, and (d) using a direct solver for the 1D-IMEX method by performing and storing LU factorizations once to obtain a constant cost for any Courant number. Without all of these improvements, explicit time integration methods turned out to be difficult to beat. We discuss in detail the IMEX infrastructure required for formulating and implementing efficient methods on manycore processors. Several parametric studies are conducted to demonstrate the gain from each of the abovementioned improvements. Lastly, we validate our results with standard benchmark problems in numerical weather prediction and evaluate the performance and scalability of the IMEX method using up to 4192 GPUs and 16 Knights Landing processors.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Processor register error correction management

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Multithreading in vector processors

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

97 MATHEMATICS AND COMPUTING↗