Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “PCB fabrication”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

33 records · Page 2

Characterization of Low-Temperature, Co-Fired Ceramic-Manufactured Electrostatic Thruster-Closeout Report

The goal of the project was to evaluate prototypes of an experimental thruster developed by the University of Arkansas (UA), Fayetteville, AR. The design under evaluation is a radio frequency (RF) electrostatic thruster that was fabricated using the low-temperature, co-fired ceramic (LTCC) materials and fabrication process. This materials system is analogous to printed circuit board (PCB) technology with the most significant difference being that the laminate is replaced by a ceramic material and the copper layer is replaced by printed sinterable silver paste. LTCC designs are baked after fabrication and assembled to realize an entirely monolithic structure with internal conductors, vias, and cavities. In this process, the LTCC electrostatic thruster (LTCC-ET) that is the subject of the present work becomes a monolithic ceramic thruster capable of withstanding temperatures in excess of 500 ºC. The UA and NASA Marshall Space Flight Center (MSFC) jointly performed prototype testing on the LTCC-ET under a NASA Cooperative Agreement Notice (CAN) award. The LTCC-ET was tested at MSFC in May 2018 over a 1-week period. There were two goals for the test program: (1) Testing to determine the operating parameters required to create plasma ignition in the test articles. This was explored by setting a propellant flowrate and increasing RF power until plasma ignition was observed. Testing was conducted with both argon and krypton. (2) Investigate the thrust and specific impulse (Isp) performance of the thruster as a function of propellant flowrate and grid voltage. This goal was not met during the project as technical challenges in maintaining stable plasma ignition arose due to stress and heating of the RF power feed. In summary, a prototype thruster design (consisting of three packaged units) was fabricated by UA and tested for the first time under vacuum conditions at MSFC to experimentally determine basic performance metrics and functionality. It was found that the design was not sufficiently optimized or robust enough in its initial iteration to support a significant test campaign or characterization program. It was concluded that the propellant outlet channels must be reduced in size with the flowpaths adjusted to increase propellant residence time in the thruster, and that the RF connector must be replaced with a version capable of handling higher power throughput and heating. However, even in its unoptimized form, a plasma could be produced in the LTCCET, demonstrating the efficacy of the design approach. The design is especially compelling due to its low cost to manufacture and, more importantly, its scalability of size and power throughput. Low cost and scalability are also important in that additional functionalities, such as thrust vectoring and plume charge neutralization, can be integrated into future designs with minimal additional cost. This project has matured the LTCC-ET development Technology Readiness Level (TRL) from 1 to 2. The low-cost RF plasma source portion of the LTCC device was matured from TRL 2 to 4 through the demonstration of RF plasma ignition under vacuum conditions.

Huang, P.-H. A.↗

Ultra-Wideband Array in PCB for Millimeter-Wave 5G and ISM

Next generation 5G mobile architectures will take advantage of the millimeter-wave spectrum to deliver unprecedented bandwidth. Concurrently, there is a need to consolidate numerous disparate allocations into a single, multi-functional array. Existing arrays are either narrow-band, prohibitively expensive or cannot be scaled to these frequencies. In this paper, we present the first ultra-wideband millimeter-wave array to operate across the six 5G and ISM bands spanning 24-71 GHz. Critically, the array is realized using low-cost PCB. The design concept and optimized layout are presented, and fabrication and measurement considerations are discussed.

Ultra-Wideband Array↗

High-Throughput Microfluidic Electroporation (HTME): A Scalable, 384-Well Platform for Multiplexed Cell Engineering

Electroporation-mediated gene delivery is a cornerstone of synthetic biology, offering several advantages over other methods: higher efficiencies, broader applicability, and simpler sample preparation. Yet, electroporation protocols are often challenging to integrate into highly multiplexed workflows, owing to limitations in their scalability and tunability. These challenges ultimately increase the time and cost per transformation. As a result, rapidly screening genetic libraries, exploring combinatorial designs, or optimizing electroporation parameters requires extensive iterations, consuming large quantities of expensive custom-made DNA and cell lines or primary cells. To address these limitations, we have developed a High-Throughput Microfluidic Electroporation (HTME) platform that includes a 384-well electroporation plate (E-Plate) and control electronics capable of rapidly electroporating all wells in under a minute with individual control of each well. Fabricated using scalable and cost-effective printed-circuit-board (PCB) technology, the E-Plate significantly reduces consumable costs and reagent consumption by operating on nano to microliter volumes. Furthermore, individually addressable wells facilitate rapid exploration of large sets of experimental conditions to optimize electroporation for different cell types and plasmid concentrations/types. Use of the standard 384-well footprint makes the platform easily integrable into automated workflows, thereby enabling end-to-end automation. We demonstrate transformation of E. coli with pUC19 to validate the HTME's core functionality, achieving at least a single colony forming unit in more than 99% of wells and confirming the platform's ability to rapidly perform hundreds of electroporations with customizable conditions. This work highlights the HTME's potential to significantly accelerate synthetic biology Design-Build-Test-Learn (DBTL) cycles by mitigating the transformation/transfection bottleneck.

Gaillard, William R↗

24-71 GHz PCB Array for 5G ISM

Millimeter-wave 5G mobile architectures need to consolidate disparate frequency bands into a single, multifunctional array. Existing arrays are either narrow-band, prohibitively expensive or cannot be scaled to these frequencies. In this paper, we present the first ultra-wideband millimeter wave array to operate across six 5G and ISM bands spanning 24-71 GHz. Importantly, the array is realized using low-cost PCB. The paper presents the design and optimized layout, and discusses fabrication and measurements.

5G and ISM↗

Development of Sample Verification System for Sample Return Missions

This paper describes the development of a proof of-concept sample verification system (SVS) for in-situ mass measurement of planetary rock and soil sample in future robotic sample return missions. Our proof-of-concept SVS device contains a 10 cm diameter pressure sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in proximity to an opposing substrate with a narrow gap. The deformation of the membrane makes the gap to be narrower, resulting in increased capacitance between the two nearly parallel plates. Capacitance readout circuitry on a nearby printed circuit board (PCB) transmits data via a low-voltage differential signaling (LVDS) interface. The fabricated SVS proof-of-concept device has successfully demonstrated approximately 1pF/gram capacitance change

Electrodes↗

PCB-Based Break-Out Box

Break-out boxes (BOBs) are necessary for all electrical integration/cable checkouts and troubleshooting. Because the price of a BOB is high, and no work can be done without one, often the procedure stops, simply waiting for a BOB. A less expensive BOB would take less time in the integration, testing, and troubleshooting process. The PCB-based BOB works and looks the same as a standard JPL BOB, called Gold Boxes. The only differences between the old BOB and the new PCB-based BOB is that the new one has 80 percent of its circuitry in a printed circuit board. This process reduces the time for fabrication, thus making the BOBs less expensive. Moreover, because of its unique design, the new BOBs can be easily assembled and fixed. About 80 percent of the new PCB-based BOB is in a $22 (at the time of this reporting) custom-designed, yet commercially available PCB. This device has been used successfully to verify that BOB cables were properly made. Also, upon completion, the BOB was beeped out via a multimeter to ensure that all sockets on the connectors were properly connected to the respective banana jack. When compared to the Gold Box BOBs, the new BOB has many advantages. It is much more cost efficient, it delivers equal usability at substantially lower cost of the BOB, and the Gold Box is much heavier when compared to the new BOB. The new BOB is also a bit longer and much more versatile in that connectors are easily changeable and if a banana jack is broken, it can be replaced instead of throwing away an entire BOB.

Lee, Jason H.↗

Low temperature Zn diffusion for GaSb solar cell structures fabrication

Low temperature Zn diffusion in GaSb, where the minimum temperature was 450 C, was studied. The pseudo-closed box (PCB) method was used for Zn diffusion into GaAs, AlGaAs, InP, InGaAs and InGaAsP. The PCB method avoids the inconvenience of sealed ampoules and proved to be simple and reproducible. The special design of the boat for Zn diffusion ensured the uniformality of Zn vapor pressure across the wafer surface, and thus the uniformity of the p-GaSb layer depth. The p-GaSb layers were studied using Raman scattering spectroscopy and the x-ray rocking curve method. As for the postdiffusion processing, an anodic oxidation was used for a precise thinning of the diffused GaSb layers. The results show the applicability of the PCB method for the large-scale production of the GaSb structures for solar cells.

Sulima, Oleg V.↗

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗

NASA Tech Briefs, October 2013

Topics include: A Short-Range Distance Sensor with Exceptional Linearity; Miniature Trace Gas Detector Based on Microfabricated Optical Resonators; Commercial Non-Dispersive Infrared Spectroscopy Sensors for Sub-Ambient Carbon Dioxide Detection; Fast, Large-Area, Wide-Bandgap UV Photodetector for Cherenkov Light Detection; Mission Data System Java Edition Version 7; Adaptive Distributed Environment for Procedure Training (ADEPT); LEGEND, a LEO-to-GEO Environment Debris Model; Electronics/Computers; Millimeter-Wave Localizers for Aircraft-to-Aircraft Approach Navigation; Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces; SpaceCube Version 1.5; High-Pressure Lightweight Thrusters; Non-Magnetic, Tough, Corrosion- and Wear-Resistant Knives From Bulk Metallic Glasses and Composites; Ambient Dried Aerogels; Applications for Gradient Metal Alloys Fabricated Using Additive Manufacturing; Passivation of Flexible YBCO Superconducting Current Lead With Amorphous SiO2 Layer; Propellant-Flow-Actuated Rocket Engine Igniter; Lightweight Liquid Helium Dewar for High-Altitude Balloon Payloads; Method to Increase Performance of Foil Bearings Through Passive Thermal Management; Unibody Composite Pressurized Structure; JWST Integrated Science Instrument Module Alignment Optimization Tool; Radar Range Sidelobe Reduction Using Adaptive Pulse Compression Technique; Digitally Calibrated TR Modules Enabling Real-Time Beamforming SweepSAR Architectures; Electro-Optic Time-to-Space Converter for Optical Detector Jitter Mitigation; Partially Transparent Petaled Mask/Occulter for Visible-Range Spectrum; Educational NASA Computational and Scientific Studies (enCOMPASS); Coarse-Grain Bandwidth Estimation Scheme for Large-Scale Network; Detection of Moving Targets Using Soliton Resonance Effect; High-Efficiency Nested Hall Thrusters for Robotic Solar System Exploration; High-Voltage Clock Driver for Photon-Counting CCD Characterization; Development of the Code RITRACKS; and Enabling Microliquid Chromatography by Microbead Packing of Microchannels.

Source record↗

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗

[Activities of System Studies and Simulation, Inc.]

Contents include the following: 1. Launch Vehicle Interface Work Performed: a. S3 provided to KSC the new launch inclination targets needed for the April '04 launch date. 2. Prelaunch operations work performed: a. S3 updated the staffing plan for MSFC on-console personnel\during the Final Countdown prior to launch. 3. Software Assessment Work Performed: a. S3 evaluated and recommended approval for Program Control Board (PCB) proposed change 649 for ground software changes, as well as change 650 and 650A for Stored Program Commands. 4. Education and Public Outreach Work Performed: a. S3 continues to coordinate the effort for the design and fabrication of scale models of the GP-3 for use at the launch site, education forums, and management/technical briefings. S3 also prepared a Change Request for additional funds needed for fabrication of additional scale models. S3 drafted the planned uses of these models, including the possibility of participation in the Boston, MA showings of the traveling Einstein Exhibit. 5. Program Management Support Work Performed: a. S3 prepared the input for and closed three MSFC Centerwide Action Item Tracking Systems (CAITS) actions during this period.

Source record↗

Design of High-Power Polyphase PCB Coil Systems for Wireless Power Transfer

Printed circuit board (PCB) coils have been proposed prior for implementation as inductive wireless charging coils to minimize size and cost. Utilization of PCBs can allow for a reduced cost, improved manufacturability, and a wide range of geometric customization options. To circumvent material limitations on insulation and thermal performance, parallel paths can be implemented to divide the current per path accordingly. Within this paper, an unconventional high-power PCB coil is designed employing all possible techniques for wiring with axial and radial parallel paths with equivalent transposition to minimize circulating currents. Design studies are simulated in 3D finite element analysis (FEA) to evaluate imbalance between phases with and without transposition. Two experimental prototype coils were fabricated with measurements for self-inductance and mutual inductance between phases. These measurements were validated to be sufficiently consistent with FEA results. Additionally, a method is proposed for a two-step optimization of coupling coefficient and coil losses.

Lewis, Donovin D.↗

A Dual Linear/Circular Polarized Wideband Flat Panel Phased Array Antenna for K/Ka-band 6U CubeSat Communications Applications

Circular polarized (CP) electromagnetic waves are preferred for space-to-space and space-to-ground satellite communications (SATCOM). CubeSats with 6U sizes (1U represents a 10 cm x 10 cm x 10 cm), that will rotate together with the Moon as it orbits Earth require high gain CP antenna systems to maintain reliable communication links. Here, we have designed an 8x8 dual linear and dual circularly polarized phased array antenna (PAA) aperture that offers 22-28 GHz bandwidth, with maximum gain of 23 dBic, and beam scanning capability of ±50o with acceptable axial ratio over all scan angles. A stacked patch topology is selected to achieve wide impedance bandwidth. Each driven patch has two via feed point locations that are connected to grounded coplanar waveguide (CPW) feed structures. By utilizing phase shifters from the Anokiwave RFICs (AWMF-0165) employed for the beamforming network (BFN), we have generated both dual linear polarization and dual circular polarization in each patch. Each driven and parasitic patch is innovatively shaped to achieve excellent isolation between two feed points which, in turn, leads to low cross polarization, high efficiency and good axial ratio over the entire bandwidth. Each chip has eight outputs which feed one 2x2 sub-array consisting of four dual linear or dual circularly polarized driven patches, simultaneously. Each 2x2 sub-array of the 8x8 array are sequentially rotated which improves axial ratio performance when the antenna operates in the dual circularly polarized mode. By utilizing a mirror effect, cross-polarized fields are also improved when operated in a dual linear polarized mode. The 8x8 array aperture is simulated taking into account the effect of the multilayer printed circuit board (PCB) stack-up of the BFN and co-simulated with the power splitter outputs and chip outputs and results are compared with only passive array performance. The performance of the antenna is still excellent when non-ideal chip performances are included in the simulation analysis. The fabricated array will be tested for radiation patterns in the Antenna and Microwave Laboratory (AML) of the San Diego State University and the NASA Glenn Research Center (GRC) spherical near field chambers. The design of the 8x8 antenna array with BFN layout is shown in Fig. 1.

5G↗

ATLAS-MAP: An Automated Test Station for Gated Electronic Transport Measurements

The diversification of electronic materials in devices provides a strong incentive for methods to rapidly correlate device performance with fabrication decisions. In this work, we present a low-cost automated test station for gated electronic transport measurements of field-effect transistors. Utilizing open-source PyMeasure libraries for transparent instrument control, the “ATLAS-MAP” system serves as a customizable interface between sourcemeters and samples under test and is programmed to conduct transfer curve and van der Pauw methods with static and sweeping gate voltages. Zinc oxide transistors of variable thickness (5, 10, and 20 nm) and channel size (50 μm to 3 mm, of equal length and width) were fabricated to validate the design. Standardization of testing procedures and raw data formatting enabled automated data analysis. A detailed list of parts and code files for the system are provided.

36 MATERIALS SCIENCE↗

Evaluation of Cable Harness Post-Installation Testing

The Cable Harness Post-Installation Testing Report was written in response to an action issued by the Ares Project Control Board (PCB). The action for the Ares I Avionics & Software Chief Engineer and the Avionics Integration and Vehicle Systems Test Work Breakdown Structure (WBS) Manager in the Vehicle Integration Office was to develop a set of guidelines for electrical cable harnesses. Research showed that post-installation tests have been done since the Apollo era. For Ares I-X, the requirement for post-installation testing was removed to make it consistent with the avionics processes used on the Atlas V expendable launch vehicle. Further research for the report involved surveying government and private sector launch vehicle developers, military and commercial aircraft, spacecraft developers, and harness vendors. Responses indicated crewed launch vehicles and military aircraft perform post-installation tests. Key findings in the report were as follows: Test requirements identify damage, human-rated vehicles should be tested despite the identification of statistically few failures, data does not support the claim that post-installation testing damages the harness insulation system, and proper planning can reduce overhead associated with testing. The primary recommendation of the report is for the Ares projects to retain the practice of post-fabrication and post-installation cable harness testing.

King, M. S.↗