Heavy Ion Testing of Freescale Nano-Crystal Nonvolatile Memory
This viewgraph presentation describes radiation tests of nanocrystal (NC) memory for space systems. A nanocrystal test chip was bombarded by heavy ions from a cyclotron.
Oldham, T. R.↗
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Carbon Nanofibers Synthesized on Selective Substrates for Nonvolatile Memory and 3D Electronics
A plasma-enhanced chemical vapor deposition (PECVD) growth technique has been developed where the choice of starting substrate was found to influence the electrical characteristics of the resulting carbon nanofiber (CNF) tubes. It has been determined that, if the tubes are grown on refractory metallic nitride substrates, then the resulting tubes formed with dc PECVD are also electrically conducting. Individual CNFs were formed by first patterning Ni catalyst islands using ebeam evaporation and liftoff. The CNFs were then synthesized using dc PECVD with C2H2:NH3 = [1:4] at 5 Torr and 700 C, and approximately equal to 200-W plasma power. Tubes were grown directly on degenerately doped silicon <100> substrates with resistivity rho approximately equal to 1-5 meterohm-centimeter, as well as NbTiN. The approximately equal to 200-nanometer thick refractory NbTiN deposited using magnetron sputtering had rho approximately equal to 113 microohm-centimeter and was also chemically compatible with CNF synthesis. The sample was then mounted on a 45 beveled Al holder, and placed inside a SEM (scanning electron microscope). A nanomanipulator probe stage was placed inside the SEM equipped with an electrical feed-through, where tungsten probes were used to make two-terminal electrical measurements with an HP 4156C parameter analyzer. The positive terminal nanoprobe was mechanically manipulated to physically contact an individual CNF grown directly on NbTiN as shown by the SEM image in the inset of figure (a), while the negative terminal was grounded to the substrate. This revealed the tube was electrically conductive, although measureable currents could not be detected until approximately equal to 6 V, after which point current increased sharply until compliance (approximately equal to 50 nA) was reached at approximately equal to 9.5 V. A native oxide on the tungsten probe tips may contribute to a tunnel barrier, which could be the reason for the suppressed transport at low biases. Currents up to approximately 100 nA could be cycled, which are likely to propagate via the tube surface, or sidewalls, rather than the body, which is shown by the I-V in figure (a). Electrical conduction via the sidewalls is a necessity for dc NEMS (nanoelectromechanical system) applications, more so than for the field emission applications of such tubes. During the tests, high conductivity was expected, because both probes were shorted to the substrate, as shown by curve 1 in the I-V characteristic in figure (b). When a tube grown on NbTiN was probed, the response was similar to the approximately equal to 100 nA and is represented by curve 2 in figure (b), which could be cycled and propagated via the tube surface or the sidewalls. However, no measureable currents for the tube grown directly on Si were observed as shown by curve 3 in figure (b), even after testing over a range of samples. This could arise from a dielectric coating on the sidewalls for tubes on Si. As a result of the directional nature of ion bombardment during dc PECVD, Si from the substrate is likely re-sputtered and possibly coats the sidewalls.
Kaul, Anupama B.↗
Radiation Effects in Advanced and Emerging Nonvolatile Memories.
Abstract not provided.
Marinella, Matthew J↗
Nanometer scale nonvolatile memory device and method for storing binary and quantum memory states
Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe2) crystals onto the BN bottom layer to form a metallic layer, depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer, and depositing the graphite crystals onto the BN top layer to form a gate top layer.
Xiao, Jun↗
Nonvolatile Analog Memory
A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.
MacLeod, Todd C.↗
Analog Nonvolatile Computer Memory Circuits
In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.
MacLeod, Todd↗
Variable-Resistivity Material For Memory Circuits
Nonvolatile memory elements packed densely. Electrically-erasable, programmable, read-only memory matrices made with newly-synthesized organic material of variable electrical resistivity. Material, polypyrrole doped with tetracyanoquinhydrone (TCNQ), changes reversibly between insulating or higher-resistivity state and conducting or low-resistivity state. Thin film of conductive polymer separates layer of row conductors from layer of column conductors. Resistivity of film at each intersection and, therefore, resistance of memory element defined by row and column, increased or decreased by application of suitable switching voltage. Matrix circuits made with this material useful for experiments in associative electronic memories based on models of neural networks.
Nagasubramanian, Ganesan↗
Nonvolatile electrochemical memory at 600°C enabled by composition phase separation
Silicon-based microelectronics are limited to ~150°C and therefore not suitable for the extremely high temperatures in aerospace, energy, and space applications. While wide-band-gap semiconductors can provide high-temperature logic, nonvolatile memory devices at high temperatures have been challenging. In this work, we develop a nonvolatile electrochemical memory cell that stores and retains analog and digital information at temperatures as high as 600°C. Through correlative scanning transmission electron microscopy, we show that this high-temperature information retention is a result of composition phase separation between the oxidized and reduced forms of amorphous tantalum oxide. This result demonstrates a memory concept that is resilient at extreme temperatures and reveals phase separation as the principal mechanism that enables nonvolatile information storage in these electrochemical memory cells.
42 ENGINEERING↗
Nonvolatile random access memory
A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.
Wu, Jiin-Chuan↗
An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory
Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.
Rao, Vikram↗
Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor
The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.
Mitchell, Cody↗
Local structure effects of carbon-doping on the phase change material Ge 2 Sb 2 Te 5
Ge 2 Sb 2 Te 5 is used in phase change memory, a nonvolatile memory technology, due to its phase change properties. The primary advantage of phase change memory over the state-of-the-art (flash memory) is its simple and small device geometry, which allows for denser nodes and lower power consumption. In phase change memory, resistive heating induces fast switching between the high resistance amorphous and low resistance crystalline phases, corresponding to storage of low and high digital states, respectively. However, the instability of the amorphous phase of Ge 2 Sb 2 Te 5 presents issues with processing and long-term data storage; such issues can be resolved by C doping, which stabilizes the amorphous phase and raises the crystallization temperature. To better understand the local structural effects of C doping on Ge 2 Sb 2 Te 5 , in situ Ge K-edge X-ray absorption spectroscopy measurements were taken during heating of films with various C doping concentrations. Here, the range of structural transformation temperatures derived from X-ray absorption near-edge structure analysis across the C doping series proved narrower than crystallization temperatures reported in similar in situ X-ray diffraction experiments, which may reflect changes in local structure that precede long-range ordering during crystallization. In addition, rigorous extended X-ray absorption fine structure fitting across and between temperature series revealed effects of C doping on the rigidity of Ge–Te bonds at low (2 at% and 4 at%) C concentrations.
Langhout, John D.↗
Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute
Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.
2D materials↗
High-Temperature Ferroelectric Behavior of Al 0.7 Sc 0.3 N
Currently, there is a lack of nonvolatile memory (NVM) technology that can operate continuously at temperatures > 200 °C. While ferroelectric NVM has previously demonstrated long polarization retention and >10 13 read/write cycles at room temperature, the largest hurdle comes at higher temperatures for conventional perovskite ferroelectrics. Here, we demonstrate how AlScN can enable high-temperature (>200 °C) nonvolatile memory. The c-axis textured thin films were prepared via reactive radiofrequency magnetron sputtering onto a highly textured Pt (111) surface. Photolithographically defined Pt top electrodes completed the capacitor stack, which was tested in a high temperature vacuum probe station up to 400 °C. Polarization–electric field hysteresis loops between 23 and 400 °C reveal minimal changes in the remanent polarization values, while the coercive field decreased from 4.3 MV/cm to 2.6 MV/cm. Even at 400 °C, the polarization retention exhibited negligible loss for up to 1000 s, demonstrating promise for potential nonvolatile memory capable of high–temperature operation. Fatigue behavior also showed a moderate dependence on operating temperature, but the mechanisms of degradation require additional study.
36 MATERIALS SCIENCE↗
A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture
The flourishing development of neural networks that require exponentially growing amounts of data has presented an elevated demand for memory footprint. To address this, researchers have been exploring hardware accelerators with innovative memory architectures like 3D memory. These 3D memory architectures offer enhanced storage capacity and processing capabilities, at a cost of rising on-chip temperature during operation. Hafnium Zirconium Oxide (HZO) based Ferroelectric Random Access Memory (FeRAM) is a promising nonvolatile memory candidate in neural network hardware accelerators for its outstanding write performance and reliability. However, its implementation in the architecture regarding the temperature-dependent ferroelectric switching behavior has not been well studied. In this work, we study the thermal impacts on polarization switching through experimental devices and simulation results. We conduct the circuit and architecture-level simulations to showcase that one can exploit this temperature rise to reduce FeRAM's write voltage and write energy due to its unique temperature-activated polarization switching mechanisms. As the on-chip temperature increases to 351K (ambient temperature at 300K) due to neural network workloads, the access energy per bit can be reduced by 27.6% when a dynamic write voltage is applied.
36 MATERIALS SCIENCE↗