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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Off-state magnetoresistance in long-channel germanium Schottky-barrier MOSFETs

An increasing magnetic field perpendicular to an undoped semiconductor surface at low temperature is known to strengthen the binding of localized electrons to stationary ions, as the wavefunction's tails evolve from exponential to Gaussian. It is also known that application of a high bias voltage to a depleted semiconductor can liberate bound charge and induce a large drop in electrical resistance. We connect these established results to experimental electrical transport measurements on off-state germanium Schottky-barrier metal–oxide–semiconductor field-effect transistor (MOSFETs) with an aluminum oxide insulating dielectric and platinum germanide contacts. We make measurements at the three distinct orientations of the magnetic field with respect to the substrate and the current. At 6 K, we observe sharp attenuation of current by more than 2 orders of magnitude, within 60 mT, at a crossover magnetic field perpendicular to the substrate. A 1 T magnetic field attenuates the current by more than 4 orders of magnitude. The strength of the attenuation and the value of the crossover field are controlled by both the gate–source and drain–source voltages. The attenuation is much weaker when the magnetic field is parallel to the current. Finally, we orient the magnetic field parallel to the substrate, but perpendicular to the current, allowing us to distinguish charge hopping at the oxide interface from charge hopping in the bulk. In conclusion, this large off-state magnetoresistance can be exploited for cryogenic magnetic- and photo-detection, and for high-bias, low-leakage MOSFETs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Temperature-Agnostic Pt/Au Ohmic Contacts on n -Type Gallium Nitride for Self-Aligned MOSFETs

Five alternative metals are investigated as ohmic contacts to n-GaN including Cr/Au, Mo/Au, Pt/Au, Pd/Au, and Ge/Au. Ti-based contacts are traditionally used for ohmic contacts on n-GaN. However, conventional Ti/Al/Ni/Au metallization is found to be incompatible with a self-aligned process for GaN trench MOSFETs due to wet etch restrictions. Therefore, an alternative metallization is needed that is unreactive to the etch chemistry used in the self-aligned process. Additionally, the contact should remain ohmic following anneal at 900 °C so that contact formation can precede the anneal required for p-dopant activation. Here, in the present work, an n-GaN bilayer, consisting of a thin heavily doped contact layer (n 0 = 1 × 10 20 cm −3 ) atop a thick lesser doped layer, is used to demonstrate ohmic contacts of alternative metals with low specific contact resistance and extended thermal budget. Cr/Au ohmic contacts are demonstrated up to anneal temperatures of 800 °C, an increase of 200 °C compared to the highest known reports for Cr/Au contacts on n-GaN. Pt/Au metallization is demonstrated as an ohmic contact to n-GaN for the first time and exhibits true temperature-agnostic behavior up to anneal temperatures of 900 °C with specific contact resistance that is near parity with Ti/Al/Ni/Au. The temperature-agnostic behavior of Pt/Au ohmic contacts on the n-GaN bilayer, in addition to chemical compatibility with the self-aligned process, positions Pt/Au contacts as a key enabling element for self-aligned trench MOSFETs on GaN.

Reilly, Kevin James [Sandia National Laboratories ↗
DOE OSTI2021

A Double-side Cooled SiC MOSFET Power Module with Sintered-silver Interposers: I. Design, Simulation, Fabrication, and Performance Characterization

Planar, double-side cooled power modules are emerging in electric-drive inverters because of their low profile, better heat extraction, and lower package parasitic inductances. However, there is still concern about their reliability due to the rigid interconnection between the device chips and two substrates of the power module. In this paper, a porous interposer made of low-temperature sintered silver is introduced to reduce the thermo-mechanical stresses in the module. A double-side cooled half-bridge module consisting of two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using the sintered-Ag instead of solid copper interposers, our simulation results showed that at a total power loss of 200 W, the thermo-mechanical stress at the most vulnerable interfaces (interposer-attach layer) was reduced by 42 % and in the SiC MOSFET by 50 % with a trade-off of only 3.6 % increase in junction temperature. The sintered-Ag interposers were readily fabricated into desired dimensions without post-machining and did not require any surface finishing for die-bonding and substrate interconnection by silver sintering. Here, the porous interposers were also deformable under a low force or pressure, which helped to accommodate chip thickness and/or substrate-to-substrate gap variations in the planar module structure, thus simplifying module fabrication. Experimental results on the electrical performance of the fabricated SiC modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.

42 ENGINEERING↗
DOE OSTI2023

Improved noise performance from the next-generation buried-channel p-MOSFET SiSeROs

The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. In our earlier work, we characterized a number of first prototype SiSeROs with the MOSFET transistor channels at the surface layer. An equivalent noise charge (ENC) of around 15 electrons root mean square (RMS) was obtained. In this work, we examine the first buried-channel SiSeRO. Here we have achieved substantially improved noise performance of around 4.5 electrons root mean square (RMS) and a full width half maximum (FWHM) energy resolution of 132 eV at 5.9 keV, for a readout speed of 625 kpixel/s. We also discuss how digital filtering techniques can be used to further improve the SiSeRO noise performance. Additional measurements and device simulations will be essential to further mature the SiSeRO technology. This new device class presents an exciting new technology for the next-generation astronomical X-ray telescopes requiring fast, low-noise, radiation-hard megapixel imagers with moderate spectroscopic resolution.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2020

High voltage MOSFET devices and methods of making the devices

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

42 ENGINEERING↗
DOE OSTI2024

Double-Side Cooled 1.2kV, 300A SiC MOSFET Phase-leg Modules for 200 kW, > 100 kW/L Traction Inverters

The packaging of a double-side cooled 1.2 kV, 149 A SiC phase-leg modules has been reported in recent years for making 100 kW, 100 kW/L traction inverters. Each phase-leg module consists of two SiC MOSFETs, one per switch position. Six of the phase-leg modules are assembled into a segmented inverter configuration to meet the power and power density requirement. In this work, the layout of the phase-leg module was redesigned to include four of the SiC MOSFETs, two per switch position, with the aim of doubling the power to 200 kW and increasing the power density beyond 100 kW/L, but with only a 10.25% footprint increase. Key features of the packaging technology developed in the previous work were implemented in the current work, which include silver sintering for chip bonding and porous silver inter-posts for bonding device source pads to substrate. Parasitic extraction simulation showed that the four-chip module has a low parasitic inductance of 4.7 nH, like the two-chip module. Static characterization of the four-chip prototypes showed a low average on-resistance of 9 mΩ and a low average leakage current of 5 nA at Vds of 1.2 kV.

Zhang, Zichen↗
DOE OSTI2024

A Multi-Metrics In Situ Aging Detector for SiC Power MOSFET Modules with Full Driver-Integration Capability

In this paper, the concept and prototype of an aging detector for silicon carbide (SiC) power metal oxide semiconductor field effect transistor (MOSFET) are proposed and described. It leverages the resonant peak values of gate-source voltage at different instants during the switching transients to decode the change of multiple aging indicators, such as the increases of on-state resistance and threshold voltage. Modeling-based analysis is conducted to support the idea. The detector can be fully integrated into gate drivers without any additional connection to the power stage and is functional during normal power stage operation. A prototype unit was built, and preliminary tests were conducted to validate the idea and the practicality of the detector.

aging↗
DOE OSTI2022

Probing the Atomic Scale Mechanisms of Time Dependent Dielectric Breakdown in Si/SiO 2 MOSFETs (June 2022)

Here we report on an atomic-scale study of trap generation in the initial/intermediate stages of time-dependent dielectric breakdown (TDDB) in high-field stressed (100) Si/SiO2 MOSFETs using two powerful analytical techniques: electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR). We find the dominant EDMR-sensitive traps generated throughout the majority of the TDDB process to be silicon dangling bonds at the (100) Si/SiO2 interface (Pb0 and Pb1 centers) for both the spin-dependent recombination (SDR) and trap-assisted tunneling (SDTAT) processes. We find this generation to be linked to both changes in the calculated interface state densities as well as changes in the NZFMR spectra for recombination events at the interface, indicating a redistribution of mobile magnetic nuclei which we conclude could only be due to the redistribution of hydrogen at the interface. Additionally, we observe the generation of traps known as E’ centers in EDMR measurements at lower experimental temperatures via SDR measurements at the interface. Our work strongly suggests the involvement of a rate-limiting step in the tunneling process between the silicon dangling bonds generated at the interface and the ones generated throughout the oxide.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Design Considerations for High-Voltage Insulated Gate Drive Power Supply for 10-kV SiC MOSFET Applied in Medium-Voltage Converter

High-performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This article focuses on the design of a high-voltage-insulated GDPS for the 10-kV silicon carbide MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including interwinding capacitance, load voltage regulation rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. Furthermore, the test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load voltage regulation rate, higher conversion efficiency, and simpler control circuit.

42 ENGINEERING↗
DOE OSTI2026

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗
DOE OSTI2021

Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.

4H-SiC↗
DOE OSTI2020

Hardware Design and Demonstration of a 100kW, 99% Efficiency Dual Active Half Bridge Converter Based on 1700V SiC Power MOSFET

High efficiency, high density and galvanically isolated power converters are attractive for numerous medium voltage high power applications. This paper presents a 1.5kVdc, 100kW bidirectional Dual Active Half Bridge (DAHB) using newly developed 1.7kV SiC MOSFET modules. The DAHB achieved an efficiency of 98.6% at full load of 100kW and a maximum of 99% at 45kW, operating as an isolated DC/DC converter. The converter also achieved an efficiency of 97.8% operating as an isolated DC/AC inverter. An optimized PCB-based busbar design has significantly reduced the voltage overshoot across the device, making the design suitable for 1500Vdc input application such as 1500V PV inverters. Typical partial discharge inception voltage (PDIV) of the optimized PCB busbar is 1.7kVpeak with total charge <10pC. The power density of the DAHB converter is 1.8MVA/m 3 which is much higher than traditional two-stage industry products. The DAHB converter can be used as a building block for a 4.16kV/1MVA utility scale PV systems with input parallel and output series configuration.

Xu, Wei↗
DOE OSTI2023

Design and Demonstration of an 850 V dc to 13.8 kV ac 100 kW Three-phase Four-wire Power Conditioning System Converter Using 10 kV SiC MOSFETs

In this paper, an 850 V dc to 13.8 kV ac 100 kW modular multilevel three-phase four-wire dc/ac converter based on 10 kV SiC MOSFETs is designed and demonstrated. The design considerations of key components, including the dc-link, device cooling, gate driver, isolated gate driver power supply (GDPS), medium voltage (MV) ac filter inductor, MV and medium frequency transformer, and the mechanical design are discussed. Two converters are designed, and two prototypes are developed, to study the converter paralleling operation and scalability. Both converters are fully tested up to their voltage and power ratings. However, the two converters are not identical. Based on the design and test results of the first converter, the MV power stage, transformer design, GDPS, as well as the low voltage power stage in the second converter are improved for smaller size and/or higher efficiency. Compared to the version 1 converter, the version 2 converter achieves 49% volume reduction and 2 percentage point efficiency improvement, with a peak efficiency of 98.4% at the rated power.

Li, Haiguo↗
DOE OSTI2020

Design of 1500V/200kW 99.6% Efficiency Dual Active Bridge Converters Based on 1700V SiC Power MOSFET Module

High efficiency, high density and galvanically isolated power converters are attractive for medium voltage high power applications. This paper presents a 1.5kV/200kW bidirectional Dual Active Bridge (DAB) converter using a newly developed 1.7kV SiC MOSFET module. The intended application is megawatt scale solid state transformer (SST) and 1500V PV inverter application using modular architecture. One novel model to estimate the turn-off loss using snubber capacitors is proposed and experimentally verified. An optimized PCB-based busbar design is introduced to reduce the voltage overshoot across the SiC device, making the design suitable for 1.5kVdc applications. The mechanism of how the optimized PCB-based busbar can reduce the voltage overshoot is quantitatively interpreted and experimentally verified. The DAB converter achieved an efficiency of 98.85% at 200kW and a maximum of 99.53% at 60kW. The maximum efficiency for series-resonant mode is 99.6% at 85kW and 99.3% at 200kW. The power density is 26W/inch3 (1.6MW/m3) which is much higher than traditional industry products.

Xu, Wei↗
DOE OSTI2021

3-D Full-Band Monte Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire MOSFETs

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices.

42 ENGINEERING↗
DOE OSTI2020

A Novel Voltage Balancing Control With dv/dt Reduction for 10-kV SiC MOSFET-Based Medium Voltage Modular Multilevel Converter

Using high voltage (HV) silicon carbide (SiC) power semiconductors in a modular multilevel converter (MMC) is promising because it results in fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulsewidth modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of the single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this article, limiting the maximum dv/dt to the dv/dt of a single power semiconductor and also maintaining the voltage balance performance. Furthermore, the proposed voltage balancing control is experimentally validated in a 10-kV SiC mosfet based MMC with four submodules per arm.

42 ENGINEERING↗
DOE OSTI2024

An Organic, Direct Bonded Copper, Multi-Layered, Ultra-Low Inductance Package for High-Power UWBG MOSFETs

The most common metalized substrates used in high-power switching packages consist of a ceramic layer such as Aluminum Nitride (AlN) sandwiched between two copper layers. Ceramic substrates are used because it has the key characteristic of having high dielectric strength while being thermally conductive. A large drawback to ceramic substrates is that they do not allow for a multi-layered circuit design. By replacing the traditional ceramic substrate with organic direct bonded copper (ODBC) we can open a wide range of possibilities when it comes to power module layout such as multi-layered circuits and double-sided cooling. Both benefits are critical while packaging high-performance Gallium Oxide (Ga2O3) MOSFETs. Because of Ga2O3's relatively poor thermal conductivity, a double-sided cooled package becomes necessary. Therefore, the use of ODBC provides the flexibility to fabricate copper traces carrying much higher currents, and by creating a multi-layered package, we can drastically reduce the parasitic inductance inside the power module. Achieving lower parasitic inductance is critical for an ultra-fast Ga2O3 package to avoid excessive voltage overshoot and ringing. Using ODBC, we have designed novel packages capable of handling the challenges presented by fast Ga2O3 switching. Using multi-physics modeling software, we can validate our design before building the prototype. Due to the simple process parameters needed to work with ODBC, we can rapidly create prototypes without using external vendors. This flexibility allows us to quickly design, build, and validate highly complex switching power modules to accommodate next generation, Ga2O3 switching devices.

ADVANCED PROPULSION SYSTEMS,ENGINEERING↗