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Results for “MEMORY STORAGE UNIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1965

Molecules and memory.

Molecules and memory, discussing role of RNA as switching element in memory processes

NEURON TRANSMISSION↗
NASA NTRS1999

EXPRESS Rack Technology for Space Station

The EXPRESS rack provides accommodations for standard Mid-deck Locker and ISIS drawer payloads on the International Space Station. A design overview of the basic EXPRESS rack and two derivatives, the Human Research Facility and the Habitat Holding Rack, is given in Part I. In Part II, the design of the Solid State Power Control Module (SSPCM) is reviewed. The SSPCM is a programmable and remotely controllable power switching and voltage conversion unit which distributes and protects up to 3kW of 12OVDC and 28VDC power to payloads and rack subsystem components. Part III details the development and testing of a new data storage device, the BRP EXPRESS Memory Unit (BEMU). The BEMU is a conduction-cooled device which operates on 28VDC and is based on Boeing-modified 9GB commercial disk-drive technology. In Part IV results of a preliminary design effort for a rack Passive Damping System (PDS) are reported. The PDS is intended to isolate ISPR-based experiment racks from on-orbit vibration. System performance predictions based on component developmental testing indicate that such a system can provide effective isolation at frequencies of 1 Hz and above.

Davis, Ted B.↗
NASA NTRS1978

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Hayes, P. J.↗
NASA NTRS1973

The data processor from the small scientific satellite

A reprogrammable data system aboard a small scientific satellite is described that samples and processes magnetospheric measurements for transmission to the ground. The lightweight configuration of the data system is made up of the program memory, data storage, input/output module, and a central processing unit. The system is designed for multiple missions.

Mccain, H. G.↗
NASA NTRS1981

Selecting an image analysis minicomputer system

Factors to be weighed when selecting a minicomputer system as the basis for an image analysis computer facility vary depending on whether the user organization procures a new computer or selects an existing facility to serve as an image analysis host. Some conditions not directly related to hardware or software should be considered such as the flexibility of the computer center staff, their encouragement of innovation, and the availability of the host processor to a broad spectrum of potential user organizations. Particular attention must be given to: image analysis software capability; the facilities of a potential host installation; the central processing unit; the operating system and languages; main memory; disk storage; tape drives; hardcopy output; and other peripherals. The operational environment, accessibility; resource limitations; and operational supports are important. Charges made for program execution and data storage must also be examined.

Danielson, R.↗
NASA NTRS1989

FFTs in external or hierarchical memory

A description is given of advanced techniques for computing an ordered FFT on a computer with external or hierarchical memory. These algorithms (1) require as few as two passes through the external data set, (2) use strictly unit stride, long vector transfers between main memory and external storage, (3) require only a modest amount of scratch space in main memory, and (4) are well suited for vector and parallel computation. Performance figures are included for implementations of some of these algorithms on Cray supercomputers. Of interest is the fact that a main memory version outperforms the current Cray library FFT routines on the Cray-2, the Cray X-MP, and the Cray Y-MP systems. Using all eight processors on the Cray Y-MP, this main memory routine runs at nearly 2 Gflops.

Bailey, David H.↗