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At least 37 records · Page 2

Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

Rogers, David↗

System and method for memory allocation in a multiclass memory system

A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

97 MATHEMATICS AND COMPUTING↗

Reducing Memory Consumption in Calico with Shared Memory

This document details the work to reduce memory consumption in Calico. Calico is SimTools’ Constructive Solid Geometry (CSG) and geometry painting library. It is primarily used to paint material volume fractions in the Eulerian meshes of the physics codes. Calico provides point-in-body checks for the geometry supplied by an Oso model, which are then aggregated by the host codes. In addition, Calico can be used to build Oso models and is used by Ingen for that purpose. Oso models, and thus Calico, provide support for various CSG primitives such as spheres, cylinders, surfaces generated by rotating tabular curve data, and STL files as well as binary combinations of those primitives. Prior to refactoring Calico will run out of memory on CTS-1 machines when 36 MPI ranks are used per node when reading STL models on the order of 1.5 GB. This limitation is a bottleneck in designer workflow. This problem has been alleviated through the use of data structures to both reduce memory consumption and to leverage MPI-3 shared memory. This report details the data structures targeted for refactoring in Calico, the methods and implementation details for reducing memory consumption and leveraging shared memory, and results for one test problem. Results show a memory reduction when loading a 1 GB STL file by a factor of 27.5, from 93.4 to 3.4 GB.

97 MATHEMATICS AND COMPUTING↗

Practice makes imperfect: Working memory training can harm recognition memory performance

There is a great deal of debate concerning the benefits of working memory (WM) training and whether that training can transfer to other tasks. Although a consistent finding is that WM training programs elicit a short-term near-transfer effect (i.e., improvement in WM skills), results are inconsistent when considering persistence of such improvement and far transfer effects. In this study, we compared three groups of participants: a group that received WM training, a group that received training on how to use a mental imagery memory strategy, and a control group that received no training. Although the WM training group improved on the trained task, their posttraining performance on nontrained WM tasks did not differ from that of the other two groups. In addition, although the imagery training group’s performance on a recognition memory task increased after training, the WM training group’s performance on the task decreased after training. Participants’ descriptions of the strategies they used to remember the studied items indicated that WM training may lead people to adopt memory strategies that are less effective for other types of memory tasks. Our results indicate that WM training may have unintended consequences for other types of memory performance.

59 BASIC BIOLOGICAL SCIENCES↗

Experimental Characterization of OpenMP Offloading Memory Operations and Unified Shared Memory Support

The OpenMP specification recently introduced support for unified shared memory, allowing implementation to leverage underlying system software to provide a simpler GPU offloading model where explicit mapping of variables is optional. Support for this feature is becoming more available in different OpenMP implementations on several hardware platforms. A deeper understanding of the different implementation’s execution profile and performance is crucial for applications as they consider the performance portability implications of adopting a unified memory offloading programming style. This work introduces a benchmark tool to characterize unified memory support in several OepnMP compilers and runtimes, with emphasis on identifying discrepancies between different OpenMP implementations as to how they various memory allocation strategies interact with unified shared memory. The benchmark tool is used to characterize OpenMP compilers on three leading High Performance Computing platforms supporting different CPU and device architectures. The benchmark tool is used to assess the impact of enabling unified shared memory on the performance of memory-bound code, highlighting implementation differences that should be accounted for when applications consider performance portability across platforms and compilers.

Elwasif, Wael↗

A Cerebellar-model Associative Memory as a Generalized Random-access Memory

A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

Kanerva, Pentti↗

Compressing data for storage in cache memories in a hierarchy of cache memories

An electronic device includes at least one compression-decompression functional block and a hierarchy of cache memories with a first cache memory and a second cache memory. The at least one compression-decompression functional block receives data in an uncompressed state, compresses the data using one of a first compression or a second compression, and, after compressing the data, provides the data to the first cache memory for storage therein. When the data is retrieved from the first cache memory to be stored in the second cache memory, when the data is compressed using the first compression, the compression-decompression functional block decompresses the data to reverse effects of the first compression on the data, thereby restoring the data to the uncompressed state and provides the data compressed using the second compression or in the uncompressed state to the second cache memory for storage therein.

97 MATHEMATICS AND COMPUTING↗

Defense mechanism for non-volatile memory based main memory

A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.

SeyedzadehDelcheh, SeyedMohammad↗

JACC.shared: Leveraging HPC Metaprogramming and Performance Portability for Computations That Use Shared Memory GPUs

In this work, we present JACC.shared, a new feature of Julia for ACCelerators (JACC), which is the performanceportable and metaprogramming model of the just-in-time and LLVM-based Julia language. This new feature allows JACC applications to leverage the high-performance computing (HPC) capabilities of high-bandwidth, on-chip GPU memory. Historically, exploiting high-bandwidth, shared-memory GPUs has not been a priority for high-level programming solutions. JACC.shared covers that gap for the first time, thereby providing a highlevel, portable, and easy-to-use solution for programmers to exploit this memory and supporting all current major accelerator architectures. Well-known HPC and AI workloads, such as multi/hyperspectral imaging and AI convolutions, have been used to evaluate JACC.shared on two exascale GPU architectures hosted by some of the most powerful US Department of Energy supercomputers: Perlmutter (NVIDIA A100) and Frontier (AMD MI250X). The performance evaluation reports speedup of up to 3.5× by adding only one line of code to the base codes, thus providing important accelerators in a simple, portable, and transparent way and elevating the programming productivity and performance-portability capabilities for Julia/JACC HPC, AI, and scientific applications.

Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.

bio-inspired, energy storage (including batteries ↗

Analysis of memory use for improved design and compile-time allocation of local memory

Trace analysis techniques are used to study memory referencing behavior for the purpose of designing local memories and determining how to allocate them for data and instructions. In an attempt to assess the inherent behavior of the source code, the trace analysis system described here reduced the effects of the compiler and host architecture on the trace by using a technical called flattening. The variables in the trace, their associated single-assignment values, and references are histogrammed on the basis of various parameters describing memory referencing behavior. Bounds are developed specifying the amount of memory space required to store all live values in a particular histogram class. The reduction achieved in main memory traffic by allocating local memory is specified for each class.

Mcniven, Geoffrey D.↗

A general model for memory interference in a multiprocessor system with memory hierarchy

The problem of memory interference in a multiprocessor system with a hierarchy of shared buses and memories is addressed. The behavior of the processors is represented by a sequence of memory requests with each followed by a determined amount of processing time. A statistical queuing network model for determining the extent of memory interference in multiprocessor systems with clusters of memory hierarchies is presented. The performance of the system is measured by the expected number of busy memory clusters. The results of the analytic model are compared with simulation results, and the correlation between them is found to be very high.

Taha, Badie A.↗

Memory states in small arrays of Josephson junctions

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

97 MATHEMATICS AND COMPUTING↗

Resistive memory for radiation resistant non-volatile memory (NSTRF Final Report)

As space programs increase in number and scope, there is an increasing need for radiation-hardened electronic devices and circuits. In particular, missions to high-radiation environments, such as Europa, would greatly benefit from improved radiation hardness in electronic devices. In pursuit of this goal, resistive memory (RRAM) devices were fabricated at SUNY Polytechnic Institute and evaluated for radiation hardness. Our objectives were to produce RRAM devices resistant to high levels of radiation damage and to demonstrate that these devices would improve mission lifetime in high-radiation environments. Furthermore, the underlying mechanisms of radiation were investigated to provide recommendations for radiation-hardening RRAM devices, which could be applied to any candidate RRAM devices being considered for space applications. Devices were fabricated using several fabrication approaches, including patterning by shadow mask, photolithography-based etching, and photolithography-based liftoff. In each of these cases, total ionizing dose (TID) effects and displacement damage dose (DDD) effects were measured. TID effects from exposure to a 60Co gamma source were not observed to cause changes in device resistance or switching parameters in any experiments, with each device tested to at least 20 Mrad(Si). DDD was measured as radiation-generated oxygen vacancies per cm 3 since oxygen vacancies are generally considered to be the active species involved in switching these devices. The lowest DDD level that caused a device to change resistance state was 10 21 vacancies per cm 3 , and most devices failed at 1022 vacancies per cm 3 . This is an extremely high DDD level, even for RRAM devices, which have been reported to fail in the range of 10 17 -10 20 vacancies per cm 3 . For comparison, an example flash memory device failed at 10 15 vacancies per cm 3 . Vendor-fabricated devices with a similar composition to our own were also tested against TID and DDD. The vendor-fabricated devices did not exhibit changes due to TID, up to the tested level of 30 Mrad(Si). Meanwhile, vendor devices exhibited resistance state changes at 10 21 vacancies per cm 3 , similar to our own devices. These results indicate that Ta0x-based RRAM devices may be particularly resilient to both TID and DDD effects. The very high tolerance to radiation effects is most likely due to the high intrinsic concentration of oxygen vacancies within our devices. Based on X-ray photoelectron spectroscopy (XPS) measurements, there are approximately 10 22 oxygen vacancies per cm 3 in our devices as deposited. Most devices failed when the radiation-induced vacancies reached this level, indicating suggesting that a high intrinsic vacancy concentration protects against lower levels of displacement damage. High vacancy concentration likely also protects against TID by facilitating leakage of trapped charge out of the oxide. The use of a thin switching oxide (25 nm Ta0 x , for our devices) is also expected to improve radiation hardness, as there is less room for charge trapping. Therefore, those wishing to produce very radiation-tolerant RRAM devices can probably achieve this by using a thin oxide that contains a high intrinsic concentration of oxygen vacancies. Our devices appear to be very tolerant of radiation effects, and would greatly increase the expected lifetime of a mission to Europa or another high-radiation target compared to flash memory devices. The similar radiation performance of vendor-fabricated devices is promising for adoption of RRAM devices as radiation-hardened memory devices for use in space. With continued commercial development of these devices, RRAM devices are strong candidates for next-generation memories that are inherently rad-hard.

36 MATERIALS SCIENCE↗

Recoverable distributed shared virtual memory - Memory coherence and storage structures

This paper examines the problem of implementing rollback recovery in multicomputer distributed shared virtual memory environments, in which the shared memory is implemented in software and exists only virtually. A user-transparent checkpointing recovery scheme and new twin-page disk storage management are presented to implement a recoverable distributed shared virtual memory. The checkpointing scheme is integrated with the shared virtual memory management. The twin-page disk approach allows incremental checkpointing without an explicit undo at the time of recovery. A single consistent checkpoint state is maintained on stable disk storage. The recoverable distributed shared virtual memory allows the system to restart computation from a previous checkpoint due to a processor failure without a global restart.

Wu, Kun-Lung↗

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

97 MATHEMATICS AND COMPUTING↗