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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗
DOE OSTI2025

Dtc Commercialization Software Package

This code is the complete software and firmware components supporting DTC model radios H2 and BluSDR6. This software package contains all the hardware boot up code/config files(BSP), user space Linux code (Web, Network, MAC (media access control) & drivers), the field programable gate array HDL (hardware description language) code and the build environment to compile and organize these components together to work in the aforementioned radios. Additional details of these components are as follows: • Hardware support components o Board support package and configuration files o uBoot • Linux Components: o The web components include the user interface for setup, configuration, and status components of the system. o Vulture code configures the radio’s IP network, configures radio parameters and runs the MAC layer of the radio. • The Field Programmable Gate Array HDL contains hardware drivers, interface logic to go between the software to the physical layer and the radio hardware as well as the logic for the physical layer of the radio. • Build environment includes compilers and config files that compile and organize all the other components to be able to be run on the radios.

Loera, Jose [Idaho National Laboratory (INL), Idah↗
DOE OSTI2025

LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.

Farooq, M. A. [Arizona State U., Tempe]↗
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

3D printable feedstock inks for signal control or computation

In one aspect the present disclosure relates to a 3D printed signal control backbone apparatus. The apparatus may have a filament including a first material section and a plurality of second material sections. The first material section is bounded on opposing ends by the second material sections. The first material section is formed by an ink having a percolating network of a plurality of chiplets infused in a non-conductive polymer. The plurality of chiplets form electrically responsive elements imparting a predetermined logic function and which are responsive to a predetermined electrical signal. The second material sections are formed by an ink which is electrically conductive.

Murialdo, Maxwell↗
DOE OSTI2025

Atomic Structure, Dynamics, Changes in Chemical Bonding and Semiconductor-Metal Transition in Sb 2 Se 3 : A Remarkable Material for Quantum Networks and Energy Applications

Antimony sesquiselenide has become an outstanding functional material for photovoltaics, energy storage and transformation, memory and photonic applications. Sb 2 Se 3 is one of the most successful emerging solar light absorbers and has also been identified as a highly promising ultralow-loss phase-change material (PCM) for next-generation coherent nanophotonic processors, photonic tensor cores, quantum and neuromorphic networks. Unlike benchmark telluride PCMs, Sb 2 Se 3 features a quasi-one-dimensional (1D) crystalline structure consisting of (Sb 4 Se 6 ) ∞ ribbons, lacks the typical PCM chemical bonding, and undergoes an extended semiconductor-metal transition above the melting point. Consequently, the origin of high optical contrast between crystalline (SET) and amorphous (RESET) logic states remains elusive and presents a significant challenge. Using high-energy X-ray diffraction and Raman spectroscopy over a wide temperature range, supported by first-principles simulations and complemented by thermal, optical and electrical measurements, as well as by 121 Sb-Mossbauer spectroscopy, the quasi-1D network of orthorhombic antimony sesquiselenide was found to undergo significant evolution in amorphous and supercooled Sb 2 Se 3 , leading to lower coordination, shorter interatomic distances and a higher p-electron density on antimony, indicating changes in chemical bonding. The observed novel Sb 2 Se 3 nanocrystalline polymorph, characterized by trigonal antimony coordination and more isolated Sb-Se ribbons, could help reduce multiple trapping defect states in the bandgap, which are typical of orthorhombic Sb 2 Se 3 , thereby enhancing the power-conversion efficiency of photovoltaic devices. Semimetallic and metallic liquid Sb 2 Se 3 exhibit a gradual transformation into a denser 2D and/or 3D network with higher antimony coordination. Localized electron states in the pseudogap are becoming extended, leading to an increase in electronic conductivity σ following the relationship σ ∝ N(E F ) 2 . Liquid Sb 2 Se 3 also appears to be strongly fragile, with a nonmonotonic change in viscosity and higher atomic mobility in the metallic liquid. Furthermore, these results explain extraordinary functionalities of Sb 2 Se 3 for photonic and energy applications.

antimony↗
DOE OSTI2026

End-To-End Decentralized Transmission Line Protection in IBR-Dominated Weak Grids Using Interpretable Data-Driven Methods

Traditional transmission line protection relies on predictable synchronous-based fault signatures, which frequently fail under the non-standard, current-limited fault characteristics of Inverter-Based Resources (IBRs). This study investigates how to achieve secure, communication-free fault isolation in IBR-dominated weak grids without relying on opaque, computationally heavy "black-box" machine learning algorithms. To address this, we propose a novel, standalone, and inherently interpretable data-driven protection framework. Unlike centralized methods requiring multi-terminal communication, this decentralized approach relies solely on local measurements using a hierarchical linear-kernel Support Vector Machine (SVM). The methodology decomposes the protection task into four sequential stages that mimic traditional protection elements: fault detection and fault direction identification, fault type classification, zone classification, and location estimation. This multi-stage architecture allows for specialized feature engineering at each stage, combining high computational efficiency with logic traceability. The framework's end-to-end performance was validated via C-code and PSCAD/EMTDC co-simulation, utilizing a real-world utility network and an OEM black-box IBR model. The proposed relay achieves 97.2% overall accuracy and provides a reliable trip decision within a 2.5-cycle window. The results confirm 100% accuracy in fundamental fault detection, reliable zone selectivity across low to moderate fault resistances, and robust security against non-fault transients, proving its immediate viability for integration into commercial numerical relays.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2026

Knowledge gaps for neuromorphic ionic computing

BACKGROUND Neuromorphic computing, inspired by the human brain’s ability to process information efficiently, represents a transformative approach to computation. In this Review, we explore the emerging field of neuromorphic ionic computing, which leverages ionic conduction and coupling to mimic neural processes, and identify critical knowledge gaps that must be addressed to realize its full potential. A central theme of the discussion is energy efficiency, a challenge that is both a limitation and an opportunity for this technology. Although complementary metal-oxide semiconductor (CMOS)–based neuromorphic technologies have made strides in scaling to billions of neurons and are increasingly applied in artificial intelligence and numerical computing, they remain orders of magnitude behind the human brain in terms of connectivity and energy efficiency. Neuromorphic ionic computing promises to overcome these limitations by leveraging the distinct architectural and operational principles of the brain. Our brains achieve this energy efficiency by combining several key features: using the same network elements to store and process information; using an incredibly complex and massively interconnected three-dimensional (3D) network of locally active elements that enables sparsity, robustness in the presence of noise, adaptation, and life-long learning; computing at comparatively low voltage and frequency; and last, taking advantage of a plethora of ions and small molecules as information carriers. Here, we propose that ionic computing systems can take advantage of similar features to achieve substantial gains in energy efficiency. ADVANCES Since the first reports of neuromorphic ionic behavior in nanofluidic channels, we have witnessed an explosion of reports that used ionic devices to produce synaptomimetic behaviors. However, achieving the goals of ionic computing requires not only implementation of much more sophisticated device functionality but also overcoming fundamental barriers in materials science, device architecture, and system integration. Current ionic devices, even those incorporating state-of-the-art materials, still suffer from limited functionality and stability, which restrict their performance and increase energy demands. Developing new materials with enhanced ionic properties is essential to overcome these limitations. Similarly, the design of neuromorphic devices must evolve to leverage the particular advantages of ionic processes. Existing architectures often follow a single-information-carrier logic of conventional electronics or are constructed of mesoscale fluidics, failing to capitalize on the energy-efficient mechanisms inherent to ionic systems or implement the multiple-information-carrier paradigm. Current neuromorphic chips focus on large-scale networks of analog memory elements based on mechanisms such as charge trap (flash), filamentary, phase change, or spin, which are built on top of a network of artificial CMOS neurons. Although such prototype networks have achieved impressive performance, it is difficult to envision how they can implement the key features such as massive connectivity, sophisticated plasticity, adaptability, sparsity, and “multichromatic” computing. Although small-scale devices have demonstrated promising results, integrating them, maintaining energy efficiency, and implementing temperature control as systems grow in complexity and size to computationally relevant scale remain major hurdles. Furthermore, interfacing neuromorphic ionic devices with existing computing technologies presents technical and conceptual challenges that will require innovative approaches that combine insights from neuroscience, materials science, and engineering. OUTLOOK Despite these challenges, the potential impact of neuromorphic ionic computing is profound with potential applications ranging from artificial intelligence to robotics and beyond. We also argue that neuromorphic ionic computing systems should not, at least in the beginning, compete with CMOS technologies but rather should focus on applications that require extreme energy efficiency with chemical and/or biological compatibility, such as biomedical applications (for example, brain-computer interfaces), environmental monitoring, and agricultural and food applications. Ultimately, this Review highlights the crucial role of interdisciplinary collaboration in advancing the field. Neuromorphic ionic computing is not merely a technological innovation; it represents a substantial step toward sustainable computation, aligning with the growing demand for energy-conscious solutions in a world that is increasingly reliant on data and computation.

Neuromorphic↗
DOE OSTI2025

Radiation Effects on Network on Chips (NoC) Laboratory Directed Research and Development (LDRD) project

This project was motivated by State-of-the-Art (SOTA) technology that incorporates Network on Chips (NOC) for efficient data communication across the various computer kernels. For example, on the AMD Versal Field Programmable Gate Arrays (FPGA), an NoC has been incorporated for fast data communication from the programmable logic and other computer kernels (processing system, adaptable intelligence engines, etc.). The radiation effects on the legacy technology of this FPGA, such as the programmable logic, are well understood, and established methods exist to measure cross-sections when new families/generations are released; however, newly incorporated technologies, such as the NoC, are not fully understood and could introduce new failure points into the mission space.

36 MATERIALS SCIENCE↗
DOE OSTI2025

ARM-IRL: Adaptive Resilience Metric Quantification Using Inverse Reinforcement Learning

The resilience of safety-critical systems is gaining importance due to the rise in cyber and physical threats, especially within critical infrastructure. Traditional static resilience metrics may not capture dynamic system states, leading to inaccurate assessments and ineffective responses to cyber threats. This work aims to develop a data-driven, adaptive method for resilience metric learning. We propose a data-driven approach using inverse reinforcement learning (IRL) to learn a single, adaptive resilience metric. The method infers a reward function from expert control actions. Unlike previous approaches using static weights or fuzzy logic, this work applies adversarial inverse reinforcement learning (AIRL), training a generator and discriminator in parallel to learn the reward structure and derive an optimal policy. The proposed approach is evaluated on multiple scenarios: optimal communication network rerouting, power distribution network reconfiguration, and cyber–physical restoration of critical loads using the IEEE 123-bus system. The adaptive, learned resilience metric enables faster critical load restoration in comparison to conventional RL approaches.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Leveraging FPGA Advantages for Quicker Data Processing for LBNF

The Long Baseline Neutrino Facility (LBNF) will deliver a 2.4 MW muon neutrino beam from Fermilab to the Deep Underground Neutrino Experiment (DUNE), requiring unprecedented precision in beamline alignment to achieve DUNE's neutrino oscillation measurement goals. Vertical misalignments of beamline components as small as 0.5 mm can contribute 6-7\% uncertainty in predicted neutrino flux, necessitating sub-0.1 mm alignment monitoring capabilities. The Horn Location Sensor (HLS) system employs frequency sweep interferometry (FSI) in a distributed hydrostatic leveling network to achieve the required precision under harsh radiation conditions up to 5000 kRad/year. Traditional FSI implementations suffer from laser sweep nonlinearities that degrade resolution and require computationally intensive post-processing corrections using gas reference cells. This work presents a real-time FPGA-based implementation of the HLS data acquisition and processing system using a sweep tracker interferometer for dynamic sweep linearization. The system utilizes a PYNQ-Z2 FPGA with programmable logic implementing parallel 16k-point FFT processing across four channels, synchronized by the sweep tracker signal to eliminate post-processing requirements. Spectral performance testing demonstrates significant improvements in peak sharpness compared to traditional fixed-frequency digitization. The FPGA implementation enables real-time displacement monitoring with processing speeds orders of magnitude faster than software-based approaches, essential for the operational requirements of LBNF's eventual distributed sensor network. This advancement in real-time FSI processing directly supports DUNE's precision neutrino physics program by providing the rapid feedback necessary for maintaining stringent beamline alignment tolerances during high-power beam operations.

Rossel, Jacob↗
DOE OSTI2025

Real-Time FPGA Implementation For Frequency Sweep Interferometry In The LBNF Complex

The Long Baseline Neutrino Facility (LBNF) will deliver a 2.4 MW muon neutrino beam from Fermilab to the Deep Underground Neutrino Experiment (DUNE), requiring unprecedented precision in beamline alignment to achieve DUNE's neutrino oscillation measurement goals. Vertical misalignments of beamline components as small as 0.5 mm can contribute 6-7\% uncertainty in predicted neutrino flux, necessitating sub-0.1 mm alignment monitoring capabilities. The Horn Location Sensor (HLS) system employs frequency sweep interferometry (FSI) in a distributed hydrostatic leveling network to achieve the required precision under harsh radiation conditions up to 5000 kRad/year. Traditional FSI implementations suffer from laser sweep nonlinearities that degrade resolution and require computationally intensive post-processing corrections using gas reference cells. This work presents a real-time FPGA-based implementation of the HLS data acquisition and processing system using a sweep tracker interferometer for dynamic sweep linearization. The system utilizes a PYNQ-Z2 FPGA with programmable logic implementing parallel 16k-point FFT processing across four channels, synchronized by the sweep tracker signal to eliminate post-processing requirements. Spectral performance testing demonstrates significant improvements in peak sharpness compared to traditional fixed-frequency digitization. The FPGA implementation enables real-time displacement monitoring with processing speeds orders of magnitude faster than software-based approaches, essential for the operational requirements of LBNF's eventual distributed sensor network. This advancement in real-time FSI processing directly supports DUNE's precision neutrino physics program by providing the rapid feedback necessary for maintaining stringent beamline alignment tolerances during high-power beam operations.

Rossel, A. Jacob [Fermilab; Unlisted]↗
DOE OSTI2024

Low‐Volume Cores for Fabrication of Compact, Versatile, and Intelligent Soft Systems

Abstract This study introduces the low‐volume core (LVC) fabrication method, which enables the monolithic molding of compact, complex, versatile, and intelligent soft robotic systems. This method uses thin and flexible thermoplastic sheets to mold internal chambers in soft fluidic actuators, valves, and circuits. The LVC fabrication method creates low‐volume networks in soft actuators (LV‐net actuators) that can be made with compact and complex geometries, enabling both low actuation volume input and multi‐degree‐of‐freedom actuators. LVC fabrication can also be used for compact, completely soft, and monolithic logic components (valves with low‐volume core, also called as LV valves) to provide directional resistance as well as a switching mechanism that enables fluidic logic in soft systems. The compatibility of the fabrication methods for both soft actuators and valves facilitates the creation of compact, integrated, and versatile soft robotic systems with embodied intelligence. This study introduces two examples of such intelligent soft robotic systems that integrate both LV‐net actuators and LV valves to demonstrate capability for complex system fabrication.

Yu, Qifan↗
DOE OSTI2025

A Novel Protection Scheme for Unbalanced Faults in Inverter Dominated Networks: A Computationally Efficient Algorithm for Entry-Level Relays

Microgrids are now a common practice in distribution systems to increase resilience and reliability. However, microgrid protection remains a critical challenge, considering its requirement to operate in both grid connected and islanded, and the variability in fault characteristics under each mode of operation. This paper presents unbalanced power (S unb ) based fault detection algorithm, which considers local voltage and current unbalances to determine faults in the system. S unb is a computationally efficient fault detection algorithm that is suitable for implementation in the programmable logic of entry level protective relays. In addition, the difference in current and voltage unbalance (D n ) is used to determine the fault type. The proposed method demonstrates high sensitivity and selectivity for line-to-ground (LG), line-to-line (LL), and double line-to-ground (LLG) faults, representing the most common faults in distribution systems. It also allows relay coordination with upstream and downstream protection devices in both island and grid connected operation, while preserving grading margins. The same pickup and time multiplier settings of a particular relay for both modes of operation eliminates the need for adaptive settings, which rely on communication networks. Validation was performed with a hardware-in-the-loop (HIL) setup using Typhoon HIL real time simulator interfaced with three entry-level, SEL 751 relays. Results confirmed the algorithm’s ability to discriminate fault conditions, and determine the fault type under both operating modes, maintain fast detection times, and ensure proper protection coordination.

fault classification↗
DOE OSTI2026

White-Rabbit-Disciplined FPGA Readout for Fermilab Timing Events

Fermilab's accelerator timing links broadcast short event codes to thousands of devices at once, but the links themselves carry no absolute notion of time; that comes separately from a White Rabbit reference. This work builds the piece that ties the two together on a single board. On a Xilinx Kria KR260 (Zynq UltraScale+), the programmable logic decodes a real Fermilab TCLK link, stamps every event with an absolute White-Rabbit \{sec, ns\} UTC time, and reads the timestamped stream out over AXI4-Lite; a thin Linux process on the same die publishes each event into a Redis stream on the control network. To exercise the full chain on one board, the decoded events are re-encoded as gigabit ACLK, transmitted out an SFP+ optical port, looped back over a short fiber jumper, and decoded again on the same timeline, and are additionally mirrored as an ACLK-Lite Manchester waveform for benchtop probing. Across sustained, multi-day testing against real Fermilab TCLK, the pipeline has decoded, timestamped, and published hundreds of millions of events with practically zero loss, and folding the timestamped stream on the 60-second accelerator supercycle recovers the machine's periodic structure directly from the published data.

Rossel, Jacob [Fermilab; UC, Berkeley (main)] (ORC↗
DOE OSTI2026

A Single-Board Fermilab Timing Pipeline on the Xilinx KR260: Decode, Timestamp, Publish, Mirror

Full-width abstract \renewcommand{\maketitlehookd}{% \begin{abstract} \noindent Fermilab's accelerator timing links broadcast short event codes to thousands of devices at once, but the links themselves carry no absolute notion of time; that comes separately from a White Rabbit reference. This work builds the piece that ties the two together on a single board. On a Xilinx Kria KR260 (Zynq UltraScale+), the programmable logic decodes a real Fermilab TCLK link, stamps every event with an absolute White-Rabbit \{sec, ns\} UTC time, and reads the timestamped stream out over AXI4-Lite; a thin Linux process on the same die publishes each event into a Redis stream on the control network. To exercise the full chain on one board, the decoded events are re-encoded as gigabit ACLK, transmitted out an SFP+ optical port, looped back over a short fiber jumper, and decoded again on the same timeline, and are additionally mirrored as an ACLK-Lite Manchester waveform for benchtop probing. Across sustained, multi-day testing against real Fermilab TCLK, the pipeline has decoded, timestamped, and published hundreds of millions of events with practically zero loss, and folding the timestamped stream on the 60-second accelerator supercycle recovers the machine's periodic structure directly from the published data.

Rossel, Jacob [UC, Berkeley; Fermilab] (ORCID:0009↗
DOE OSTI2025

Evaluating Function-as-a-Service (FaaS) frameworks for the Accelerator Control System

As particle accelerator control systems evolve in complexity and scale, the need for responsive, scalable, and cost-effective computational infrastructure becomes increasingly critical. Function-as-a-Service (FaaS) offers an alternative to traditional monolithic architecture by enabling event-driven execution, automatic scaling, and fine-grained resource utilization. This paper explores the applicability and performance of FaaS frameworks in the context of a modern particle accelerator control system, with the objective of evaluating their suitability for short lived and triggered workloads. In this paper, we evaluate prominent open-source FaaS platforms in executing functional logic, triggers, and diagnostics routines. Evaluation metrics consist of cold-start latency, scalability, performance, integration with other open-source tools like Kafka. Experimental workloads were designed to simulate real-world control tasks when implemented as stateless FaaS functions. These workloads were benchmarked under various invocation loads and network conditions. Self-hosted FaaS platforms, when deployed within accelerator networks, offer greater control over execution environment, better integration with legacy systems, and support for real-time guarantees when paired with message queues. Based on lessons learned and evaluation metrics, this paper describes reliability of the FaaS framework for the Accelerator Control Systems (ACS).

Jaikar, A. [Fermilab] (ORCID:0000000332046217)↗
DOE OSTI2026

Agentic traffic intelligence: Augmented human-in-the-loop scenario generation for microscopic traffic simulation

Traditional microscopic traffic simulation generation often relies on static datasets and manual design, limiting its ability to simulate complex conditions easily. This paper presents a novel framework, Agentic Traffic Intelligence, which combines human approval large language models (LLMs), the Real-Twin tool, and multi-agent systems to perform realistic microscopic traffic simulation scenario generation. The proposed framework incorporates human-in-the-loop (HIL) control, retrieval-augmented generation (RAG), and multi-agent control mechanisms. HIL mechanisms are used to guide multiple LLMs focused on attributes for microscopic simulation generation and to improve the interpretability and transparency of LLM execution for users. RAG enhances context extraction by dynamically integrating external knowledge sources for traffic scenario generation foundations. A multi-agent architecture with supervisory control coordinates the interaction of simulation components, including traffic simulators, control logic, and calibration tools. This enables the synthesis of simulation-ready scenarios that reflect dynamic demand profiles and behavior controls. Furthermore, the framework fuses multisource traffic data with unstructured context and supports iterative refinement through interactive user feedback. Validated through microscopic simulation using Simulation of Urban Mobility, the generated scenarios demonstrate high-fidelity network generation with inflow and turn movement and behavioral calibration, offering a robust and efficient tool for stress-testing and optimizing urban mobility systems.

Hierarchical multi-agent control↗