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At least 37 records · Page 2

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DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗

DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗

DOE OSTI2025

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗

DOE OSTI2026

TTDAQ: A Continuous Flow, Timing and Trigger DAQ System

Final Scientific/Technical Report for DOE Award DE-SC0019581, “TTDAQ: A Continuous Flow, Timing and Trigger DAQ System.” The report summarizes Telluric Labs’ Phase II STTR work developing silicon-photonic building blocks for a software-defined, continuous-flow, trigger-less data acquisition system for next-generation high-energy and nuclear-physics detectors. The project focused on radiation-hard photonic integrated circuits, remote optical illumination, dense wavelength-division multiplexing, and a differential microring-resonator transceiver architecture designed to improve high-speed optical link stability and bandwidth. The report describes project objectives, technical accomplishments, AIM Photonics tape-outs, bench characterization, radiation-hardness testing, deferred integration work, and potential applications beyond physics readout.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2026

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗

DOE OSTI2025

Scalable low-loss cryogenic packaging of quantum memories in CMOS-foundry processed photonic chips

Optically linked solid-state quantum memories such as color centers in diamond are a promising platform for distributed quantum information processing and networking. Photonic integrated circuits (PICs) have emerged as a crucial enabling technology for these systems, integrating quantum memories with efficient electrical and optical interfaces in a compact and scalable platform. Packaging these hybrid chips into deployable modules while maintaining low optical loss and resiliency to temperature cycling is a central challenge to their practical use. We demonstrate a packaging method for PICs using surface grating couplers and angle-polished fiber arrays that is robust to temperature cycling, offers scalable channel count, applies to a wide variety of PIC platforms and wavelengths, and offers pathways to automated high-throughput packaging. Using this method, we show optically and electrically packaged quantum memory modules integrating all required qubit controls on chip, operating at millikelvin temperatures with <3 dB losses achievable from fiber to quantum memory for the TE 0 mode at a wavelength of 737 nm.

Bernson, Robert [Tyndall National Institute, Cork ↗

DOE OSTI2025

Designs for scalable construction of hybrid quantum photonic cavities

Nanophotonic resonators are central to numerous applications, from efficient spin–photon interfaces to laser oscillators and precision sensing. A leading approach consists of photonic crystal (PhC) cavities, which have been realized in a wide range of dielectric materials. However, translating proof-of-concept devices into a functional system entails a number of additional challenges, inspiring new approaches that combine resonators with wavelength-scale confinement and high quality factors; scalable integration with integrated circuits and photonic circuits; electrical or mechanical cavity tuning; and, in many cases, a need for heterogeneous integration with functional materials such as III–V semiconductors or diamond color centers for spin–photon interfaces. Here we introduce a concept that generates a finely tunable PhC cavity at a selected wavelength between two heterogeneous optical materials whose properties satisfy the above requirements. The cavity is formed by stamping a hard-to-process material with simple waveguide geometries on top of an easy-to-process material consisting of dielectric grating mirrors and active tuning capability. We simulate our concept for the particularly challenging design problem of multiplexed quantum repeaters based on arrays of cavity-coupled diamond color centers, achieving theoretically calculated unloaded quality factors of 106, mode volumes as small as 1.2(λ/neff)3, and maintaining >60% total on-chip collection efficiency of fluorescent photons. We further introduce a method of low-power piezoelectric tuning of these hybrid diamond cavities, simulating optical resonance shifts up to ∼760 GHz and color center fluorescence tuning of 5 GHz independent of cavity tuning. These results will motivate integrated photonic cavities toward larger scale systems-compatible designs.

Greenspon, Andrew S. (ORCID:0000000296317568)↗

DOE OSTI2025

Optoelectronic polymer memristors with dynamic control for power-efficient in-sensor edge computing

Abstract As the demand for edge platforms in artificial intelligence increases, including mobile devices and security applications, the surge in data influx into edge devices often triggers interference and suboptimal decision-making. There is a pressing need for solutions emphasizing low power consumption and cost-effectiveness. In-sensor computing systems employing memristors face challenges in optimizing energy efficiency and streamlining manufacturing due to the necessity for multiple physical processing components. Here, we introduce low-power organic optoelectronic memristors with synergistic optical and mV-level electrical tunable operation for a dynamic “control-on-demand” architecture. Integrating signal sensing, featuring, and processing within the same memristors enables the realization of each in-sensor analogue reservoir computing module, and minimizes circuit integration complexity. The system achieves 97.15% fingerprint recognition accuracy while maintaining a minimal reservoir size and ultra-low energy consumption. Furthermore, we leverage wafer-scale solution techniques and flexible substrates for optimal memristor fabrication. By centralizing core functionalities on the same in-sensor platform, we propose a resilient and adaptable framework for energy-efficient and economical edge computing.

Optics↗

DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

Alcalde Bessia, Fabricio↗

DOE OSTI2025

A virtual Frisch-grid geometry-based CZT gamma detector for in-field radioisotope identification

Here, we present a Virtual Frisch-Grid geometry-based CZT gamma detector developed for identifying different radioisotopes over an energy range from a few keV up to 2 MeV, and useful for efficient characterization of CZT crystals. The detector is built with a 3 x 3 matrix of CZT crystals, each measuring approximately 6 mm x 6 mm x 15 mm. The charge generated within the sensor’s active volume is read out via an anode connected directly to the AVG3_Dev integrated circuit. A current signal induced by charge drift is collected on side pads of the crystals, enabling reconstruction of a 3D interaction position. This paper discusses the design, development, and performance of the standalone, mobile detector system, which integrates the AVG3_Dev readout IC developed at Brookhaven National Laboratory, a high-speed FPGA-based with per-channel digital signal processing, and embedded system capabilities. The device is compact, battery-powered, and supports wireless data streaming, making it suitable for field operations for radioisotope identification.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗

DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗

DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗

DOE OSTI2026

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗

DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗

DOE OSTI2025

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented in brief. Current documentation is available at https://github.com/SpacelyProject/spacely-docs.

Quinn, Adam [Fermilab]↗