System implementation and operations session: Implementation and operation of yield forecasting and crop growth stage estimation
There are no author-identified significant results in this report.
Mccrary, D.↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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System implementation and operations session: System implementation and approaches used for generation of crop production reports
There are no author-identified significant results in this report.
Hatch, R. E.↗
System implementation and operations session: Accuracy assessment, system implementation and operation
There are no author-identified significant results in this report.
Pitts, D. E.↗
Implementation and Synthesis of Math Library Functions
Achieving speed and accuracy for math library functions like exp, sin, and log is difficult. This is because low-level implementation languages like C do not help math library developers catch mathematical errors, build implementations incrementally, or separate high-level and low-level decision making. This ultimately puts development of such functions out of reach for all but the most experienced experts. To address this, we introduce MegaLibm, a domain-specific language for implementing, testing, and tuning math library implementations. MegaLibm is safe, modular, and tunable. Implementations in MegaLibm can automatically detect mathematical mistakes like sign flips via semantic wellformedness checks, and components like range reductions can be implemented in a modular, composable way, simplifying implementations. Once the high-level algorithm is done, tuning parameters like working precisions and evaluation schemes can be adjusted through orthogonal tuning parameters to achieve the desired speed and accuracy. MegaLibm also enables math library developers to work interactively, compiling, testing, and tuning their implementations and invoking tools like Sollya and type-directed synthesis to complete components and synthesize entire implementations. MegaLibm can express 8 state-of-the-art math library implementations with comparable speed and accuracy to the original C code, and can synthesize 5 variations and 3 from-scratch implementations with minimal guidance.
97 MATHEMATICS AND COMPUTING↗
Comparing computational times for simulations when using PBPK model template and stand-alone implementations of PBPK models
Introduction We previously developed a PBPK model template that consists of a single model “superstructure” with equations and logic found in many physiologically based pharmacokinetic (PBPK) models. Using the template, one can implement PBPK models with different combinations of structures and features. Methods To identify factors that influence computational time required for PBPK model simulations, we conducted timing experiments using various implementations of PBPK models for dichloromethane and chloroform, including template and stand-alone implementations, and simulating four different exposure scenarios. For each experiment, we measured the required computational time and evaluated the impacts of including various model features (e.g., number of output variables calculated) and incorporating various design choices (e.g., different methods for estimating blood concentrations). Results We observed that model implementations that treat body weight and dependent quantities as constant (fixed) parameters can result in a 30% time savings compared with options that treat body weight and dependent quantities as time-varying. We also observed that decreasing the number of state variables by 36% in our PBPK model template led to a decrease of 20–35% in computational time. Other factors, such as the number of output variables, the method for implementing conditional statements, and the method for estimating blood concentrations, did not have large impacts on simulation time. In general, simulations with PBPK model template implementations of models required more time than simulations with stand-alone implementations, but the flexibility and (human) time savings in preparing and reviewing a model implemented using the PBPK model template may justify the increases in computational time requirements. Conclusion Our findings concerning how PBPK model design and implementation decisions impact computational speed can benefit anyone seeking to develop, improve, or apply a PBPK model, with or without the PBPK model template.
Bernstein, Amanda S.↗
Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode
In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.
Lin, Shu↗
Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode
In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.
Lin, Shu↗
Implementation of Adaptive Digital Controllers on Programmable Logic Devices
Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.
Gwaltney, David A.↗
Implementation of Adaptive Digital Controllers on Programmable Logic Devices
Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.
Gwaltney, David A.↗
Know Your Enemy - Implementation of Bioremediation within a Suspected DNAPL Source Zone Following High-Resolution Site Characterization at Contractors Road Heavy Equipment Area, Kennedy Space Center, Florida
The National Aeronautics and Space Administration (NASA), Kennedy Space Center (KSC), has adopted high-resolution site characterization (HRSC) sampling techniques during baseline sampling prior to implementation of remedies to confirm and refine the conceptual site model (CSM). HRSC sampling was performed at Contractors Road Heavy Equipment Area (CRHE) prior to bioremediation implementation to verify the extent of the trichloroethene (TCE) dense non-aqueous phase liquid (DNAPL) source area (defined as the area with TCE concentrations above 1% solubility) and its daughter product dissolved plume that had been identified during previous HRSC events. The results of HRSC pre-bioremediation implementation sampling suggested that the TCE source area was larger than originally identified during initial site characterization activities, leading to a design refinement to improve electron donor distribution and increase the likelihood of achieving remedial objectives. Approach/Activities: HRSC was conducted from 2009 through 2014 to delineate the vertical and horizontal extent of chlorinated volatile organic compounds (CVOCs) in the groundwater. Approximately 2,340 samples were collected from 363 locations using direct push technology (DPT) groundwater sampling techniques. Samples were collected from up to 14 depth intervals at each location using a 4-foot sampling screen. This HRSC approach identified a narrow (approx. 5 to 30 feet wide), approximately 3,000 square foot TCE DNAPL source area (maximum detected TCE concentration of 160,000 micrograms per liter [micro-g/L] at DPT sampling location DPT0225). Prior to implementation of a bioremediation interim measure, HRSC baseline sampling was conducted using DPT groundwater sampling techniques. Concentrations of TCE were an order of magnitude lower than previous reported (12,000 micro-g/L maximum at DPT sampling location DPT0225) at locations sampled adjacent to previous sampling locations. To further evaluate the variability in concentrations observed additional sampling was conducted in 2016. The results identified higher concentrations than originally detected within the previously defined source area and the presence of source zone concentrations upgradient of the previously defined source area (maximum concentration observed 570,000 micro-g/L). The HRSC baseline sampling data allowed for a revision of the bioremediation design prior to implementation. Bioremediation was implemented within the eastern portion of the source area in November and December 2016 and quarterly performance monitoring was completed in March and June 2017. Reductions in CVOC concentrations from baseline were observed at all performance monitoring wells in the treatment area, and by June 2017, an approximate 95% CVOC mass reduction was observed based on monitoring well sampling results. Results/Lessons Learned: The results of this project suggest that, due to the complexity of DNAPL source zones, HRSC during pre-implementation baseline sampling in the TCE source zone was an essential strategy for verifying the treatment area and depth prior to remedy implementation. If the upgradient source zone mass was not identified prior to bioremediation implementation, the mass would have served as a long-term source for the dissolved plume.
Chrest, Anne↗
m-CUBES An efficient and portable implementation of multi-dimensional integration for gpus
The task of multi-dimensional numerical integration is frequently encountered in physics and other scientific fields, e.g., in modeling the effects of systematic uncertainties in physical systems and in Bayesian parameter estimation. Multi-dimensional integration is often time-prohibitive on CPUs. Efficient implementation on many-core architectures is challenging as the workload across the integration space cannot be predicted a priori. We propose m-Cubes, a novel implementation of the well-known Vegas algorithm for execution on GPUs. Vegas transforms integration variables followed by calculation of a Monte Carlo integral estimate using adaptive partitioning of the resulting space. m-Cubes improves performance on GPUs by maintaining relatively uniform workload across the processors. As a result, our optimized Cuda implementation for Nvidia GPUs outperforms parallelization approaches proposed in past literature. We further demonstrate the efficiency of m-Cubes by evaluating a six-dimensional integral from a cosmology application, achieving significant speedup and greater precision than the CUBA library's CPU implementation of VEGAS. We also evaluate m-Cubes on a standard integrand test suite. m-Cubes outperforms the serial implementations of the Cuba and GSL libraries by orders of magnitude speedup while maintaining comparable accuracy. Our approach yields a speedup of at least 10 when compared against publicly available Monte Carlo based GPU implementations. In summary, m-Cubes can solve integrals that are prohibitively expensive using standard libraries and custom implementations. A modern C++ interface header-only implementation makes m-Cubes portable, allowing its utilization in complicated pipelines with easy to define stateful integrals. Compatibility with non-Nvidia GPUs is achieved with our initial implementation of m-Cubes using the Kokkos framework.
Sakiotis, Ioannis↗
Field demonstration and implementation analysis of model predictive control in an office HVAC system
Model Predictive Control (MPC) is a promising technique to address growing needs for heating, ventilation, and air-conditioning (HVAC) systems to operate more efficiently and with greater flexibility. However, due to a number of factors, including the required implementation expertise, lack of high quality data, and a risk-adverse industry, MPC has yet to gain widespread adoption. While many previous studies have shown the advantages of MPC, few analyzed the implementation effort and associated practical challenges. In addition, previous work has developed an open-source, Modelica-based tool-chain that automatically generates optimal control, parameter estimation, and state estimation problems aimed at facilitating MPC implementation. Therefore, this study demonstrates usage of this tool-chain to implement MPC in a real office building, discusses practical challenges of implementing MPC, and estimates the implementation effort associated with various tasks in order to inform the development of future workflows and serve as an initial benchmark for their impact on reducing implementation effort. This study finds that the implemented MPC saves approximately 40% of HVAC energy over the existing control during a two-month trial period and that tasks related to data collection and controller deployment activities can each require as much effort as model generation.
32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager
Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.
Keymeulen, Didlier↗
Space Networking Implementation for Lunar Operations
The High-Rate Delay Tolerant Networking (HDTN) project at NASA has developed a performance optimized and open-source Delay Tolerant Networking (DTN) implementation. The primary goal is to create a scalable networking solution to increase the scientific data return rate of space missions. To reach this goal, HDTN must span multiple edge cases in space networking by including tools and configurations to accommodate a wide range of space systems. Typically, HDTN evaluations are conducted on a laboratory emulation test bed, made up of hardware accelerated x86 based systems capable of data rates over 10 Gbps. HDTN must have an effective implementation process on a wide range of systems to increase the sustainability of the design. One important implementation option is with low-level embedded systems which could be used on small robotic missions. This paper details the implementation process, benchmark testing, and performance results of HDTN in multiple configurations on Raspberry Pi 4 devices. By implementing HDTN on a Raspberry Pi 4, a process for building HDTN onto ARM processors was developed and utilized to conduct benchmark tests in multiple network configurations, achieving a data rate performance exceeding 600 Mbps. Based on these results, HDTN proved to run on small ARM based systems with slight modifications to the build procedure. These results were then extended to evaluating an implementation of the HDTN software parsed across several Raspberry Pi 4 nodes. To test this capability, HDTN was configured in a simplified cut-through setup and distributed among multiple Raspberry Pi 4 processors. This distributed architecture was benchmark tested in a similar fashion to the testing of a singular HDTN implementation. The results from the benchmark testing are used to examine how these implementation options and capabilities can expand the use cases for DTN, and particularly with small robotic missions.
Space Networking↗
Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space
On-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A modified form of the algorithm that is better suited for data from pushbroom instruments is generally appropriate for flight implementation. A scalable field programmable gate array (FPGA) hardware implementation was developed. The FPGA implementation achieves a throughput performance of 58 Msamples/sec, which can be increased to over 100 Msamples/sec in a parallel implementation that uses twice the hardware resources This paper describes the hardware implementation of the 'Modified Fast Lossless' compression algorithm on an FPGA. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for space applications.
FPGA implementation↗
Implementation of ISO 15118-202 messages within Everest EV Charging Open Source Framework [SWR-25-56]
This software implements the messages defined in the ISO 15118-202 standard within the Everest EV Charging open source framework. The protocol and messages defined in the ISO 15118-202 standard enable the exchange of additional information which is not available for exchange within the currently deployed EV/EVSE communications protocols. This information includes co-identification parameters, error message exchange and more. This fork of the everest-core repository adds a prototype of the Extensible Supply Equipment Communication Controller (SECC) Discovery Protocol (ESDP) implemented based on a draft of the ISO 15118-202 standard. This is achieved through additions and modifications to the EvseV2G module. The implementation provides a demonstration of the ESDP messages, encoding and decoding but does not include a full integration within the Everest framework. Much of the information being sent over ESDP in this implementation is set statically for the sake of demonstrating the protocol itself. This fork of the ext-switchev-iso15118 repository adds a prototype of the Extensible Supply Equipment Communication Controller (SECC) Discovery Protocol (ESDP) implemented based on a draft of the ISO 15118-202 standard. The implementation provides a demonstration of the ESDP messages, encoding and decoding but does not include a full integration within the Everest framework. Much of the information being sent over ESDP in this implementation is set statically for the sake of demonstrating the protocol itself. This fork adds the ESDP features for only the EVCC controller because that is the only portion that is utilized in the everest Software-in-the-Loop.
Watt, Ed [National Renewable Energy Laboratory (NR↗
COVID-19 prevention at institutions of higher education, United States, 2020–2021: implementation of nonpharmaceutical interventions
Background, In early 2020, following the start of the coronavirus disease 2019 (COVID-19) pandemic, institutions of higher education (IHEs) across the United States rapidly pivoted to online learning to reduce the risk of on-campus virus transmission. We explored IHEs’ use of this and other nonpharmaceutical interventions (NPIs) during the subsequent pandemic-affected academic year 2020–2021. Methods, From December 2020 to June 2021, we collected publicly available data from official webpages of 847 IHEs, including all public (n = 547) and a stratified random sample of private four-year institutions (n = 300). Abstracted data included NPIs deployed during the academic year such as changes to the calendar, learning environment, housing, common areas, and dining; COVID-19 testing; and facemask protocols. We performed weighted analysis to assess congruence with the October 29, 2020, US Centers for Disease Control and Prevention (CDC) guidance for IHEs. For IHEs offering ≥50% of courses in person, we used weighted multivariable linear regression to explore the association between IHE characteristics and the summated number of implemented NPIs. Results, Overall, 20% of IHEs implemented all CDC-recommended NPIs. The most frequently utilized NPI was learning environment changes (91%), practiced as one or more of the following modalities: distance or hybrid learning opportunities (98%), 6-ft spacing (60%), and reduced class sizes (51%). Additionally, 88% of IHEs specified facemask protocols, 78% physically changed common areas, and 67% offered COVID-19 testing. Among the 33% of IHEs offering ≥50% of courses in person, having < 1000 students was associated with having implemented fewer NPIs than IHEs with ≥ 1000 students. Conclusions, Only 1 in 5 IHEs implemented all CDC recommendations, while a majority implemented a subset, most commonly changes to the classroom, facemask protocols, and COVID-19 testing. IHE enrollment size and location were associated with degree of NPI implementation. Additional research is needed to assess adherence to NPI implementation in IHE settings.
59 BASIC BIOLOGICAL SCIENCES↗
Toward fidelity between specification and implementation
This paper describes the methods used to specify and implement a complex communications protocol that provides reliable delivery of data in multicast-capable, packet-switching telecommunication networks. The protocol, called the Reliable Multicasting Protocol (RMP), was developed incrementally by two complementary teams using a combination of formal and informal techniques in an attempt to ensure the correctness of the protocol implementation. The first team, called the Design team, initially specified protocol requirements using a variant of SCR requirements tables and implemented a prototype solution. The second team, called the V&V team, developed a state model based on the requirements tables and derived test cases from these tables to exercise the implementation. In a series of iterative steps, the Design team added new functionality to the implementation while the V&V team kept the state model in fidelity with the implementation through testing. Test cases derived from state transition paths in the formal model formed the dialogue between teams during development and served as the vehicles for keeping the model and implementation in fidelity with each other. This paper describes our experiences in developing our process model, details of our approach, and some example problems found during the development of RMP.
Callahan, John R.↗