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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Presynthetic Redox Gated Metal-to-Insulator Transition and Photothermoelectric Properties in Nickel Tetrathiafulvalene-Tetrathiolate Coordination Polymers

Photothermoelectric (PTE) materials are promising candidates for solar energy harvesting and photodetection applications, especially for near-infrared (NIR) wavelengths. Although the processability and tunability of organic materials are highly advantageous, examples of organic PTE materials are comparatively rare and their PTE performance is typically limited by poor photothermal (PT) conversion. Here, we report the use of redox-active Sn complexes of tetrathiafulvalene-tetrathiolate (TTFtt) as transmetalating agents for the synthesis of presynthetically redox tuned NiTTFtt materials. Unlike the neutral material NiTTFtt, which exhibits n-type glassy-metallic conductivity, the reduced materials Li 1.2 Ni 0.4 [NiTTFtt] and [Li(THF) 1.5 ] 1.2 Ni 0.4 [NiTTFtt] (THF = tetrahydrofuran) display physical characteristics more consistent with p-type semiconductors. The broad spectral absorption and electrically conducting nature of these TTFtt-based materials enable highly efficient NIR-thermal conversion and good PTE performance. Furthermore, in contrast to conventional PTE composites, these NiTTFtt coordination polymers are notable as single-component PTE materials. As a result, the presynthetically tuned metal-to-insulator transition in these NiTTFtt systems directly modulates their PT and PTE properties.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Let Each Quantum Bit Choose Its Basis Gates

Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX-or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea – allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on “nonstandard” Cartan trajectories that deviate from “standard” trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Furthermore, our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.

quantum computing↗
DOE OSTI2020

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10 8 . Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V TH ) and achieve positive V TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. Finally, these results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Geometric representations of braid and Yang–Baxter gates

Brick-wall circuits composed of the Yang–Baxter gates are integrable. It becomes an important tool to study the quantum many-body system out of equilibrium. To put the Yang–Baxter gate on quantum computers, it has to be decomposed into the native gates of quantum computers. It is favorable to apply the least number of native two-qubit gates to construct the Yang–Baxter gate. We study the geometric representations of all X-type braid gates and their corresponding Yang–Baxter gates via the Yang–Baxterization. We find that the braid and Yang–Baxter gates can only exist on certain edges and faces of the two-qubit tetrahedron. We identify the parameters by which the braid and Yang–Baxter gates are the Clifford gate, the matchgate, and the dual-unitary gate. The geometric representations provide the optimal decompositions of the braid and Yang–Baxter gates in terms of other two-qubit gates. We also find that the entangling powers of the Yang–Baxter gates are determined by the spectral parameters. Our results provide the necessary conditions to construct the braid and Yang–Baxter gates on quantum computers.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2016

An Integrated Gate Turnaround Management Concept Leveraging Big Data Analytics for NAS Performance Improvements

"Gate Turnaround" plays a key role in the National Air Space (NAS) gate-to-gate performance by receiving aircraft when they reach their destination airport, and delivering aircraft into the NAS upon departing from the gate and subsequent takeoff. The time spent at the gate in meeting the planned departure time is influenced by many factors and often with considerable uncertainties. Uncertainties such as weather, early or late arrivals, disembarking and boarding passengers, unloading/reloading cargo, aircraft logistics/maintenance services and ground handling, traffic in ramp and movement areas for taxi-in and taxi-out, and departure queue management for takeoff are likely encountered on the daily basis. The Integrated Gate Turnaround Management (IGTM) concept is leveraging relevant historical data to support optimization of the gate operations, which include arrival, at the gate, departure based on constraints (e.g., available gates at the arrival, ground crew and equipment for the gate turnaround, and over capacity demand upon departure), and collaborative decision-making. The IGTM concept provides effective information services and decision tools to the stakeholders, such as airline dispatchers, gate agents, airport operators, ramp controllers, and air traffic control (ATC) traffic managers and ground controllers to mitigate uncertainties arising from both nominal and off-nominal airport gate operations. IGTM will provide NAS stakeholders customized decision making tools through a User Interface (UI) by leveraging historical data (Big Data), net-enabled Air Traffic Management (ATM) live data, and analytics according to dependencies among NAS parameters for the stakeholders to manage and optimize the NAS performance in the gate turnaround domain. The application will give stakeholders predictable results based on the past and current NAS performance according to selected decision trees through the UI. The predictable results are generated based on analysis of the unique airport attributes (e.g., runway, taxiway, terminal, and gate configurations and tenants), and combined statistics from past data and live data based on a specific set of ATM concept-of-operations (ConOps) and operational parameters via systems analysis using an analytic network learning model. The IGTM tool will then bound the uncertainties that arise from nominal and off-nominal operational conditions with direct assessment of the gate turnaround status and the impact of a certain operational decision on the NAS performance, and provide a set of recommended actions to optimize the NAS performance by allowing stakeholders to take mitigation actions to reduce uncertainty and time deviation of planned operational events. An IGTM prototype was developed at NASA Ames Simulation Laboratories (SimLabs) to demonstrate the benefits and applicability of the concept. A data network, using the System Wide Information Management (SWIM)-like messaging application using the ActiveMQ message service, was connected to the simulated data warehouse, scheduled flight plans, a fast-time airport simulator, and a graphic UI. A fast-time simulation was integrated with the data warehouse or Big Data/Analytics (BAI), scheduled flight plans from Aeronautical Operational Control AOC, IGTM Controller, and a UI via a SWIM-like data messaging network using the ActiveMQ message service, illustrated in Figure 1, to demonstrate selected use-cases showing the benefits of the IGTM concept on the NAS performance.

Efficent ATM systems↗
DOE OSTI2023

Comparison of spontaneous emission in trapped-ion multiqubit gates at high magnetic fields

Penning traps have been used for performing quantum simulations and sensing with hundreds of ions and provide a promising route toward scaling up trapped ion quantum platforms because of the ability to trap and control hundreds or thousands of ions in two- and three-dimensional crystals. In both Penning traps and the more common RF Paul traps, lasers are often used to drive multi-qubit entangling operations. A leading source of decoherence in these operations is off resonant spontaneous emission. While many trapped ion quantum computers or simulators utilize clock qubits, other systems, especially those with high magnetic fields such as Penning traps, rely on Zeeman qubits, which require a more complex calculation of this decoherence. We therefore examine theoretically the impacts of spontaneous emission on quantum gates performed with trapped-ion ground state Zeeman qubits in a high magnetic field. In particular, we consider two types of gates—light-shift ($\hat{σ}^z_i$ $\hat{σ}^z_j$) gates and Mølmer-Sørensen ($\hat{σ}^x_i$ $\hat{σ}^x_j$) gates—obtained with laser beams directed approximately perpendicular to the magnetic field (the quantization axis) and compare the decoherence errors in each. Within each gate type, we also compare different operating points with regards to the detunings, polarizations, and required intensity of the laser beams used to drive the gates. Here, we show that both gates can have similar performance at their optimal operating conditions at high magnetic fields and examine the experimental feasibility of various operating points. By examining the magnetic field dependence of each gate, we demonstrate that, when the P state fine structure splitting is large compared to the Zeeman splittings, the theoretical performance of the Mølmer-Sørensen gate is significantly better than that of the light-shift gate. Additionally, for the light-shift gate, we make an approximate comparison between the fidelities that can be achieved at high fields with the fidelities of state-of-the-art two-qubit trapped ion quantum gates. We show that, with regards to spontaneous emission, the achievable fidelity of the current NIST configuration is about an order of magnitude below that of the best low-field gates, but we also discuss several alternative configurations with potential error rates that are comparable with those for state-of-the art trapped ion gates.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗