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Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.
A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.
Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.
Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.
Damage to field effect transistors by proton irradiation
Low noise amplifier design with field effect transistors, random noise characteristics, and noise measurements on commercial devices
The performance limits of carbon nanotube field-effect transistors (CNFETs) based on a recently reported process are studied by computational techniques at temperatures between 300 K and 4 K. Here, the impact of band-to-band tunneling (BTBT) and source-to-drain tunneling (SDT) is examined for devices with varying gate length through the use of simulations based on the non-equilibrium Green’s function (NEGF) formalism, and calibrated to measurements. Additionally, the case of junctionless chemical doping profiles is analyzed in contrast to electrostatic doping recently reported for test structures. The switching limits of CNFETs are further explored for devices based on carbon nanotubes (CNTs) with more favorable electronic structures.
There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.
Devices offer switching speeds greater than semiconducting counterparts. High-Tc superconducting field-effect transistors (SUPEFETs) investigated for use as electronic switches in delay-line-type microwave phase shifters. Resemble semiconductor field-effect transistors in some respects, but their operation based on different principle; namely, electric-field control of transition between superconductivity and normal conductivity.
Transition metal dichalcogenides (TMDs)-based field-effect transistors (FETs) are being investigated vigorously for their promising applications in optoelectronics. Despite the high optical response reported in the literature, most of them are studied at room temperature. To extend the application of these materials in a photodetector, particularly at a low temperature, detailed understanding of the photo response behavior of these materials at low temperatures is crucial. Here we present a systematic investigation of temperature-dependent electronic and optoelectronic properties of few-layers MoS 2 FETs, synthesized using the mechanical exfoliation of bulk MoS 2 crystal, on the Si/SiO 2 substrate. Our MoS 2 FET show a room-temperature field-effect mobility μ FE ~40 cm 2 ·V -1 ·s -1 , which increases with decreasing temperature, stabilizing at 80 cm 2 ·V -1 ·s -1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements were investigated using a continuous laser source λ = 658 nm (E = 1.88 eV) over a broad range of effective illuminating laser intensity, P eff (0.02 μW < P eff < 0.6 μW). Photoconductivity measurements indicate a fractional power dependence of the steady-state photocurrent. The room-temperature photoresponsivity (R) obtained in these samples was found to be ~2 AW -1 , and it increases as a function of decreasing temperature, reaching a maximum at T = 75 K. The optoelectronic properties of MoS 2 at a low temperature give an insight into photocurrent generation mechanisms, which will help in altering/improving the performance of TMD-based devices for various applications.
Phenomenological study of radiation damage and recovery of metal oxide semiconductor field effect transistors
Beyond-silicon technology demands ultrahigh performance field-effect transistors. Transition metal dichalcogenides provide an ideal material platform, but the device performances such as the contact resistance, on/off ratio and mobility are often limited by the presence of interfacial residues caused by transfer procedures. Here, we show an ideal residue-free transfer approach using polypropylene carbonate with a negligible residue coverage of ~0.08% for monolayer MoS 2 at the centimetre scale. By incorporating a bismuth semimetal contact with an atomically clean monolayer MoS 2 field-effect transistor on hexagonal boron nitride substrate, we obtain an ultralow Ohmic contact resistance of ~78 Ω µm, approaching the quantum limit, and a record-high on/off ratio of ~10 11 at 15 K. Further, such an ultra-clean fabrication approach could be the ideal platform for high-performance electrical devices using large-area semiconducting transition metal dichalcogenides.
We report the 1/f noise characteristics at low-frequency in graphene field-effect transistors that utilized a high- dielectric tantalum oxide encapsulated layer (a few nanometers thick) placed by atomic layer deposition on Si3N4. A low-noise level of ~ 2.2 10-10 Hz-1 has been obtained at f = 10 Hz. The origin and physical mechanism of the noise can be interpreted by the McWhorter context, where fluctuations in the carrier number contribute dominantly to the low-frequency noise. Optimizing fabrication processes reduced the number of charged impurities in the graphene field-effect transistors. The study has provided insights into the underlying physical mechanisms of the noise at low-frequency for reducing the noise in graphene-based devices.
The modulation of channel conductance in field-effect transistors (FETs) via metal-insulator-semiconductor structures has revolutionized information processing and storage. However, the limitations of silicon-based FETs in electrical switching have driven the search for new materials capable of overcoming these constraints. Electrostatic gating of competing electronic phases in a Mott material near its metal-to-insulator transition (MIT) offers the prospects of substantial modulation of the conducting electrons and electrical resistivity through small changes in band filling. While electrostatic control of the MIT has been previously reported, the advancement of Mott materials toward novel Mott-based transistors, MottFETs requires the realization of their unique physical properties in a solid-state device. In this study, we present gate control of electron correlation using a solid-state device utilizing the oxide Mott system La 1-x Sr x VO 3 as a correlated FET channel. We report on a gate resistance response that cannot be explained in a purely electrostatic framework. This behavior suggests an enhancement in effective mass and a reduction in effective carrier density as the system approaches its insulating state, consistent with theoretical predictions for Mott systems, suggesting at least 100× charge gain originating from the correlated behavior. These preliminary results pave the way toward the development of highly efficient, low-power electronic devices that could surpass the performance bottlenecks of conventional FETs by leveraging the electronic phase transitions of correlated electron systems.
An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.
Equivalent circuit for the field effect transistor made up of circuit elements can be simulated by existing computer programs.
Three double-heterojunction modulation-doped field-effect transistor structures with different channel composition are investigated theoretically. All of these transistors have an In(x)Ga(1-x)As channel sandwiched between two doped Al(0.3)Ga(0.7)As barriers with undoped spacer layers. In one of the structures, x varies from 0 from either heterojunction to 0.15 at the center of the channel quadratically; in the other two, constant values of x of 0 and 0.15 are used. The Poisson and Schroedinger equations are solved self-consistently for the electron wave function in all three cases. The results showed that the two-dimensional electron gas (2DEG) concentration in the channel of the quadratically graded structure is higher than the x = 0 one and slightly lower than the x = 0.15 one, and the mean distance of the 2DEG is closer to the center of the channel for this transistor than the other two. These two effects have important implications on the electron mobility in the channel.