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At least 37 records · Page 2

Predicting the Redshift 2 H-Alpha Luminosity Function Using [OIII] Emission Line Galaxies

Upcoming space-based surveys such as Euclid and WFIRST-AFTA plan to measure Baryonic Acoustic Oscillations (BAOs) in order to study dark energy. These surveys will use IR slitless grism spectroscopy to measure redshifts of a large number of galaxies over a significant redshift range. In this paper, we use the WFC3 Infrared Spectroscopic Parallel Survey (WISP) to estimate the expected number of H-alpha emitters observable by these future surveys. WISP is an ongoing Hubble Space Telescope slitless spectroscopic survey, covering the 0.8 - 1.65 micrometers wavelength range and allowing the detection of H-alpha emitters up to z approximately equal to 1.5 and [OIII] emitters to z approximately equal to 2.3. We derive the H-alpha-[OIII] bivariate line luminosity function for WISP galaxies at z approximately equal to 1 using a maximum likelihood estimator that properly accounts for uncertainties in line luminosity measurement, and demonstrate how it can be used to derive the H-alpha luminosity function from exclusively fitting [OIII] data. Using the z approximately equal to 2 [OIII] line luminosity function, and assuming that the relation between H-alpha and [OIII] luminosity does not change significantly over the redshift range, we predict the H-alpha number counts at z approximately equal to 2 - the upper end of the redshift range of interest for the future surveys. For the redshift range 0.7 less than z less than 2, we expect approximately 3000 galaxies per sq deg for a flux limit of 3 x 10(exp −16) ergs per sec per sq cm (the proposed depth of Euclid galaxy redshift survey) and approximately 20,000 galaxies per sq deg for a flux limit of approximately 10(exp −16) ergs per sec per sq cm (the baseline depth of WFIRST galaxy redshift survey).

Redshift↗

A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

Shao, H. M.↗

Systolic VLSI Reed-Solomon Decoder

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Shao, H. M.↗

A software simulation study of a (255,223) Reed-Solomon encoder-decoder

A set of software programs which simulates a (255,223) Reed-Solomon encoder/decoder pair is described. The transform decoder algorithm uses a modified Euclid algorithm, and closely follows the pipeline architecture proposed for the hardware decoder. Uncorrectable error patterns are detected by a simple test, and the inverse transform is computed by a finite field FFT. Numerical examples of the decoder operation are given for some test codewords, with and without errors. The use of the software package is briefly described.

Pollara, F.↗

A VLSI design of a pipeline Reed-Solomon decoder

A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

Shao, H. M.↗

A single chip VLSI Reed-Solomon decoder

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.

Shao, H. M.↗

Structure parameters in rotating Couette-Poiseuille channel flow

It is well-known that a number of steady state problems in fluid mechanics involving systems of nonlinear partial differential equations can be reduced to the problem of solving a single operator equation of the form: v + lambda Av + lambda B(v) = 0, v is the summation of H, lambda is the summation of one-dimensional Euclid space, where H is an appropriate (real or complex) Hilbert space. Here lambda is a typical load parameter, e.g., the Reynolds number, A is a linear operator, and B is a quadratic operator generated by a bilinear form. In this setting many bifurcation and stability results for problems were obtained. A rotating Couette-Poiseuille channel flow was studied, and it showed that, in general, the superposition of a Poiseuille flow on a rotating Couette channel flow is destabilizing.

Knightly, George H.↗