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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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27 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

PID-Regulated Heating System for PIP-II Reference Line

The Proton Improvement Project-2 centers on building a new superconducting linear particle accelerator (Linac) at Fermilab. At the heart of the accelerator is the reference line, a critical system that defines the ideal path for the particle beam as it passes through magnets, RF cavities, and other beamline elements. Temperature stability is crucial for the reliable operation of RF components, such as mixers and filters. Fluctuations affect key performance parameters like conversion loss, isolation, and linearity. To mitigate any drift caused by ambient temperature changes, a heating plate assembly is utilized to maintain key components at a controlled temperature of 40°C. The system utilizes an aluminum 36”x36”x0.5” heat plate powered by a MOSFET-based control circuit, delivering approximately 460 W of thermal energy through a resistor array. Real-time temperature feedback is provided by a PT100 Resistance Temperature Detector (RTD), which interfaces with a Proportional–Integral–Derivative (PID) control algorithm to maintain closed-loop temperature regulation. The control signal actively modulates the gate voltage of an N channel MOSFET, dynamically adjusting power delivery in response to deviations from the temperature setpoint. Simulations and LTspice models validate the functionality and responsiveness of the circuit under varying conditions. The prototype has successfully demonstrated stable thermal control, paving the way for integration into the PIP-II infrastructure. The final design will feature an expanded resistor array, as well as communication with a PLC for continuous data acquisition and diagnostics. This work directly supports Fermilab’s broader mission by contributing to the stability and reliability of core accelerator systems, enhancing the precision of particle beam delivery for future physics experiments.

Mosher, Alexander [Fermilab]↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2025

Does provable absence of barren plateaus imply classical simulability?

A large amount of effort has recently been put into understanding the barren plateau phenomenon. In this perspective article, we face the increasingly loud elephant in the room and ask a question that has been hinted at by many but not explicitly addressed: Can the structure that allows one to avoid barren plateaus also be leveraged to efficiently simulate the loss classically? We collect evidence-on a case-by-case basis-that many commonly used models whose loss landscapes avoid barren plateaus can also admit classical simulation, provided that one can collect some classical data from quantum devices during an initial data acquisition phase. This follows from the observation that barren plateaus result from a curse of dimensionality, and that current approaches for solving them end up encoding the problem into some small, classically simulable, subspaces. Thus, while stressing that quantum computers can be essential for collecting data, our analysis sheds doubt on the information processing capabilities of many parametrized quantum circuits with provably barren plateau-free landscapes. We end by discussing the (many) caveats in our arguments including the limitations of average case arguments, the role of smart initializations, models that fall outside our assumptions, the potential for provably superpolynomial advantages and the possibility that, once larger devices become available, parametrized quantum circuits could heuristically outperform our analytic expectations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

TEAMER: Performance mapping of Re Vision's Persistance PTO

Contains datasets from experimental measurements that were used to validate Re Vision's Persistence PTO's efficiency and performance. These measurements were obtained using a dynamometer test bench setup. The data includes open-circuit voltage and loss measurements to validate machine characteristics, efficiency mapping tests to determine the generator's performance mapping, and efficiency mapping tests to determine the converter's efficiency over the feasible operating range. This data was collected between June 2023 and September 2023. The data was collected at the National Renewable Energy Laboratory's Flatirons Campus, Colorado, United States. The data was collected using NREL's 5-kW dynamometer test bench, equipped with a torque sensor and various voltage and current sensors fed to a dedicated data acquisition system. Units for the data are included in the data file headers for each data series. A text editor or spreadsheet software such as Excel is required to view the *.csv data. The data are also provided in *.mat files. To view data plots, a Matlab script with *.mat files are provided.

16 TIDAL AND WAVE POWER↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗
DOE OSTI2025

Correcting impedance measurements for background parasitics to characterize circuit components in cryogenic environments

Predictable circuit response is a critical prerequisite for accurate electronic measurements. Here, we describe a powerful yet straightforward experimental method and analysis model that utilizes an affordable LCR meter in conjunction with an in situ parasitic-impedance background-correction procedure to measure the temperature-dependent impedance (magnitude and phase) of up to ten individual passive circuit elements in a single cryostat run. We show how the model unambiguously identified a ∼20× drop in capacitance for 22 μF 5XR multilayer ceramic capacitors cooled from 300 K to 360 mK in an environment with a parasitic capacitance of ∼300 pF. The same experimental procedure, based on a simple two-wire measurement, was also used to measure 10 and 22 pF thin-film capacitors and 100 MΩ thick-film resistors. The results showed that the resistor values increased by up to an order of magnitude when the devices were cooled from 300 K to 360 mK. Most importantly, we showed that the simple data-acquisition method, coupled with our analysis model, enabled the measurement of component parasitics, and effectively extended the accuracy of a commercial LCR meter beyond its manufacturer-guaranteed values for a wide range of measurement frequencies. We also showed that, in the current configuration, our simple approach is limited to a capacitance accuracy of ∼10 pF.

Carpenter, R. J. [Santa Clara Univ., Santa Clara, ↗
DOE OSTI2025

Obtaining Real Production Data Through On-Component Printed SIR Patterns

Cleanliness validation of printed circuit assemblies has become increasingly important as electronic assemblies become smaller, denser, and more challenging to clean, prompting an increase in reliance in custom solutions. With increasingly fast paced development cycles, long lead times and costs of quality custom surrogate test boards become prohibitive in obtaining cleanliness data that is a true representative of the final product. In this study, aerosol jet printing, an additive manufacturing technology for electronics, was used to manufacture surface insulation resistance (SIR) test structures that were evaluated on their ability to detect cleanliness defects and remain stable when clean, as well as their survivability to standard electronics wash processes. Additionally, in an effort to further increase the agility of true product testing, SIR test structures were printed directly onto ball-grid-arrays (BGAs) and tested the survivability of conformally printed leads for data acquisition. SIR test structures displayed good wash survivability on standard FR4 and BGAs, including wraparounds for on-component prints, and high sensitivity to cleanliness defects. The presented results demonstrate the feasibility of printed SIR structures as a quick-turn, highly customizable solution for wash validation with potential for increased fidelity cleanliness testing.

SIR, Additive Manufacturing, Printed Electronics, ↗
DOE OSTI2024

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.

47 OTHER INSTRUMENTATION↗