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30 records · Page 2

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile↗

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗

Silicon Micromachining for Terahertz Component Development

Waveguide component technology at terahertz frequencies has come of age in recent years. Essential components such as ortho-mode transducers (OMT), quadrature hybrids, filters, and others for high performance system development were either impossible to build or too difficult to fabricate with traditional machining techniques. With micromachining of silicon wafers coated with sputtered gold it is now possible to fabricate and test these waveguide components. Using a highly optimized Deep Reactive Ion Etching (DRIE) process, we are now able to fabricate silicon micromachined waveguide structures working beyond 1 THz. In this paper, we describe in detail our approach of design, fabrication, and measurement of silicon micromachined waveguide components and report the results of a 1 THz canonical E-plane filter.

Filter↗

Superconducting Vacuum-Gap Crossovers for High Performance Microwave Applications

The design and fabrication of low-loss wide-bandwidth superconducting vacuum-gap crossovers for high performance millimeter wave applications are described. In order to reduce ohmic and parasitic losses at millimeter wavelengths a vacuum gap is preferred relative to dielectric spacer. Here, vacuum-gap crossovers were realized by using a sacrificial polymer layer followed by niobium sputter deposition optimized for coating coverage over an underlying niobium signal layer. Both coplanar waveguide and microstrip crossover topologies have been explored in detail. The resulting fabrication process is compatible with a bulk micro-machining process for realizing waveguide coupled detectors, which includes sacrificial wax bonding, and wafer backside deep reactive ion etching for creation of leg isolated silicon membrane structures. Release of the vacuum gap structures along with the wax bonded wafer after DRIE is implemented in the same process step used to complete the detector fabrication. 

superconductor↗

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A. D↗

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan d, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 µ m thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan d with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan d ~ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan d in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· d = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· d = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A D↗

Design, Fabrication and Testing of a Modulated Metasurface Antenna at 300 GHz

This paper describes the design and realization of a modulated metasurface (MTS) antenna at 300 GHz. To overcome the hurdles associated with the use of dielectric substrates in the sub-millimeter wave range, we propose an MTS structure which consists of an array of metalized cylinders placed on a ground plane. The metal cylinders are arranged in a square lattice with sub-wavelength unit cell size. This MTS topology has been successfully used to design a spiral MTS antenna. The resulting structure has been micromachined out of a silicon wafer by means of deep reactive ion etching (DRIE). The performance of the antenna has been verified by full-wave simulations, and measurements will be available at the time of the conference.

surface waves↗

Development of Transition-Edge Sensor X-ray Microcalorimeter Linear Array for Compton Scattering and Energy Dispersive Diffraction Imaging

In this paper we present a strip transition-edge sensor microcalorimeter linear array detector developed for energy dispersive X-ray diffraction imaging and Compton scattering applications. The prototype detector is an array of 20 transition-edge sensors with absorbers in strip geometry arranged in a linear array. We discuss the fabrication steps needed to develop this array including Mo/Cu bilayer, Au electroplating, and proofof-principle fabrication of long strips of SiNx membranes. We demonstrate minimal unwanted effect of strip geometry on X-ray pulse response and showlinear relationship of 1/pulse height and pulse decay times with absorber length. For the absorber lengths studied, our preliminary measurements show energy resolutions of 40-180eV near 17 keV. Furthermore, we show that the heat flow to the cold bath is nearly independent of the absorber area and depends on the SiNx membrane geometry.

47 OTHER INSTRUMENTATION↗

Freestanding high-aspect-ratio gold masks for low-energy, phase-based x-ray microscopy

High-resolution, x-ray phase contrast microscopy, a key technique with promising potential in biomedical imaging and diagnostics, is based on narrow-slit high-aspect-ratio gold gratings. Here we present the development, fabrication details, and experimental testing of the freestanding 10 μm thick gold membrane masks with an array of 0.9–1.5 μm void slit apertures for a novel low-energy x-ray microscope. The overall mask size is 4 mm × 4 mm, with a grating pitch of 7.5 μm, 6.0–6.6 μm wide gold bars are supported by 3 μm wide crosslinks at 400 μm intervals. The fabrication process is based on gold electroplating into a silicon mold coated with various thin films to form a voltage barrier, plating base, and sacrificial layer, followed by the mold removal to obtain the freestanding gold membrane with void slit apertures. We discuss key aspects for the materials and processes, including gold structures homogeneity, residual stresses, and prevention of collapsing of the grid elements. We further demonstrate the possibility to obtain high-resolution, high contrast 2D images of biological samples using an incoherent, rotating anode x-ray tube.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

High performance MEMS micro-gyroscope

This paper reports on JPL's on-going research into MEMS gyroscopes. This paper will describe the gyroscope's fabrication-methods, a new 8-electrode layout developed to improve performance, and performance statistics of a batch of six gyroscopes recently rate tested.

green chart bias instabilities STS DRIE 8-electrod↗

Fabrication and Characteristics of Free Standing Shaped Pupil Masks for TPF-Coronagraph

Direct imaging and characterization of exo-solar terrestrial planets require coronagraphic instruments capable of suppressing star light to 10-10. Pupil shaping masks have been proposed and designed1 at Princeton University to accomplish such a goal. Based on Princeton designs, free standing (without a substrate) silicon masks have been fabricated with lithographic and deep etching techniques. In this paper, we discuss the fabrication of such masks and present their physical and optical characteristics in relevance to their performance over the visible to near IR bandwidth.

terrestrial planet finder↗