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All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Performance of the Dsa's Subcarrier Demodulation Digital Loop

The subcarrier demodulation digital loop is part of the baseband assembly. The subcarrier demodulator is a fourth-order Costas-type loop corresponding to a type 2 analog loop in terms of steady state response. The expected value and the variance of the error signal are determined as functions of the input SNR. A Nyquist sampling rate of the input signal is assumed. From the integro-difference equations a mixed s/z domain block diagram is obtained. From the loop's transfer function a set of gains for the loop filter is obtained. Also, a set of state equations is presented for future reference. Finally, the noise-equivalent bandwidths are calculated for normalized computation times of 0, 0.25 and 0.5. The subcarrier demodulator analyzed tracks a parabolic phase input with finite steady state error. Since at each update instant the loop gains are adjusted to compensate for the variations in SNR of the input signal, the noise-equivalent bandwidth is maintained constant.

Simon, M. K.↗
NASA NTRS1990

Digital Demodulator For Advanced Receiver

Complexity and cost reduced by new design for half-band filters. Digital demodulator designed for use in reception of phase- and amplitude-modulated digital signals of bandwidths up to 15 MHz on microwave carriers. System performs coherent demodulation in phase and in quadrature with carrier locked in phase to intermediate frequency of 10 MHz. Design suitable for fabrication in very-large-scale integrated circuitry. Principal innovative feature of demodulator is design of half-band digital low-pass filters that remove sum-frequency components.

Sadr, Ramin↗
NASA NTRS1990

A parallel pipelined architecture for a digital multicarrier demodulator

A parallel pipelined architecture is presented for demultiplexing and demodulating SCPC/FDMA channels in real time. Specific algorithms are selected for each of the operations necessary for multicarrier demodulation. The selection is made based on their suitability for implementation into parallel-pipelined and sharing schemes. The demodulator is programmable and uses a single hardware module which is shared among all the channels for the recovery of clock, carrier, and data, resulting in large savings of power and hardware. The system is suitable for onboard processing of signals in satellites where power and area requirements are critical. The design is illustrated for the specific case of processing 800 FDMA channels at 64 kb/s each.

Fernandes, P. J.↗
NASA NTRS1989

Advanced technology satellite demodulator development

Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.

Ames, Stephen A.↗
NASA NTRS1992

Digital Synchronous Demodulator

Digital synchronous demodulator offers further advantages over improved analog synchronous demodulator described in article, "Improved Analog Synchronous Demodulator", (GSC-13179). Suppresses ripple and other spurious outputs, but does not depend on precise matching of active and passive analog components. Offers greater speed, precision, and reliability.

Woodhouse, Christopher E.↗
NASA NTRS1991

A reconfigurable multicarrier demodulator architecture

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference.

Kwatra, S. C.↗
NASA NTRS1993

Pseudo-coherent demodulation for mobile satellite systems

This paper proposes three so-called pseudo-coherent demodulation schemes for use in land mobile satellite channels. The schemes are derived based on maximum likelihood (ML) estimation and detection of an N-symbol observation of the received signal. Simulation results for all three demodulators are presented to allow comparison with the performance of differential PSK (DPSK) and ideal coherent demodulation for various system parameter sets of practical interest.

Divsalar, Dariush↗
NASA NTRS1995

Degradation in finite-harmonic subcarrier demodulation

Previous estimates on the degradations due to a subcarrier loop assume a square-wave subcarrier. This article provides a closed-form expression for the degradations due to the subcarrier loop when a finite number of harmonics are used to demodulate the subcarrier, as in the case of the buffered telemetry demodulator. We compared the degradations using a square wave and using finite harmonics in the subcarrier demodulation and found that, for a low loop signal-to-noise ratio, using finite harmonics leads to a lower degradation. The analysis is under the assumption that the phase noise in the subcarrier (SC) loop has a Tikhonov distribution. This assumption is valid for first-order loops.

Feria, Y.↗
NASA NTRS1995

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Kwatra, S. C.↗
NASA NTRS2004

Discrete-Time Demodulator Architectures for Free-Space Broadband Optical Pulse-Position Modulation

The objective of this work is to develop discrete-time demodulator architectures for broadband optical pulse-position modulation (PPM) that are capable of processing Nyquist or near-Nyquist data rates. These architectures are motivated by the numerous advantages of realizing communications demodulators in digital very large scale integrated (VLSI) circuits. The architectures are developed within a framework that encompasses a large body of work in optical communications, synchronization, and multirate discrete-time signal processing and are constrained by the limitations of the state of the art in digital hardware. This work attempts to create a bridge between theoretical communication algorithms and analysis for deep-space optical PPM and modern digital VLSI. The primary focus of this work is on the synthesis of discrete-time processing architectures for accomplishing the most fundamental functions required in PPM demodulators, post-detection filtering, synchronization, and decision processing. The architectures derived are capable of closely approximating the theoretical performance of the continuous-time algorithms from which they are derived. The work concludes with an outline of the development path that leads to hardware.

Gray, A. A.↗
NASA NTRS1966

Diversity-lock phase demodulator

Synchronous diversity-lock phase demodulator for tracking and demodulating orthogonally polarized signals transmitted from satellites

SIGNAL TRANSMISSION↗
NASA NTRS1968

Unique frequency-shift-keyed demodulation system

Frequency-Shift-Keyed /FSK/ demodulator provides a frequency discriminator whose outputs are separate and applied to two identical decoding channels, one decoding binary ones and the other decoding binary zeros. This demodulator rejects data applied to it at any frequency higher than design.

Staloff, C.↗
NASA NTRS1977

Unbalanced quadriphase demodulator

A new and improved apparatus and method are described for demodulation of quaternary phase shift keyed (QPSK) data, particularly unbalanced QPSK. Phase adjustment of the output of a phase locked loop local oscillator is performed to reduce sensitivity to amplitude variations internal to the demodulator.

Koybayashi, H. S.↗
NASA NTRS1979

Evaluation of Costas Loops for demodulation of a spread spectrum signal for Space Shuttle up-link communications

The Space Shuttle Communication System utilizes a Costas Loop for carrier reconstruction to demodulate the Spread Spectrum signals. This design includes the increasingly popular hard limited in-phase channel which allows use of a switching type multiplier preceding the loop filter. This paper presents the development and performance of this type demodulator and includes supporting measured data.

Killen, H. B.↗
NASA NTRS1984

Demodulator and Accumulator for the High-speed Data Acquisition System

In support of nonflight project data acquisition, a high speed data acquisition system was designed. The demodulator and accumulator modules at the heart of this system perform the detection and prefiltering of data which are then further processed by a floating point systems 5210 array processor. Block diagrams of the demodulator and accumulator modules are presented.

Brokl, S. S.↗