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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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27 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Protection of Inverter-Dependent Transmission Systems (PROTECT-IT)

This presentation highlights the overall objectives of the SETO funded protection project. The main technical approaches are also highlighted. This high impact project produces multiple innovative outcomes, including comprehensive impact study of how IBR affects protection elements, simplified low-order IBR model for protection engineers, enhanced and data-driven protection design, co-design concept for coordination protection and IBRs.

14 SOLAR ENERGY↗
DOE OSTI2026

Intelligent Experiments through Real-Time AI: Fast Data Processing and Autonomous Detector Control for High-Energy Nuclear Experiments

The aim of this project is to develop software and hardware for fast real-time data processing and autonomous detector control and calibration for the sPHENIX and the future EIC experiments. Below summarizes Georgia Tech team efforts in the past year: 1. We developed a real-time clustering algorithm and FPGA-based pipeline architecture for processing fired pixel data from ALPIDE sensors in sPHENIX experiments. Our Columnar Clustering Co-Design introduces a hardware-aware, stream-friendly approach that segments pixel data by column pairs using a Column Pair Clustering (CPC) strategy, followed by Cluster Stitching to merge adjacent subclusters. Implemented in Vitis HLS, the pipeline comprises five stages—read-in, subclustering, stitching, analysis, and write-out—connected by tagged HLS streams with custom end-of-event signaling for robust synchronization. We designed a pipelined dataflow model optimized for throughput, low latency, and minimal buffering, enabling scalable clustering across events of arbitrary size. Our system maintains spatial precision via center-of-mass and shape key extraction and efficiently handles edge cases such as fragmented or nested clusters. Compared against DBSCAN in both software and hardware, our approach demonstrates competitive performance under FPGA constraints. 2. We also conducted a comprehensive algorithm-to-hardware co-design of connected component analysis tailored for sPHENIX experiments, focusing on real-time, low-latency processing using FPGAs and High-Level Synthesis (HLS). Starting from a Python-based particle tracking pipeline, the team translated the core logic—graph traversal via DFS and Union-Find—into an HLS-compatible C++ model, replacing dynamic memory and recursion with static arrays and pipelined control flow. The final design includes a fully streamed and dataflow-compatible Union-Find kernel optimized across five iterations, incorporating loop pipelining, array partitioning, AXI/FIFO interface tuning, and function flattening. Experimental results show up to 14.8× speedup over the CPU baseline, reducing per-graph latency to 1.58 μs and demonstrating strong resource efficiency with only ~7k LUTs and zero BRAM usage. The design maintains functional correctness against the Python reference using a Python-based C-simulation framework and Mean Squared Error metrics. This work validates the potential of HLS-driven FPGA designs for edge-level HEP data acquisition, laying a scalable foundation for future integration with real-time detector pipelines and multi-graph processing systems.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2026

An Integrated Framework for Memory-Centric Analysis: From Trace Collection to Co-Design

The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems—poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing certain behaviors that emerge at larger scales. These limitations reflect a processor-centric design philosophy increasingly misaligned with memory-bound workloads where detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware-assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64\%, confidence-filtered L3 errors of 9.92\%, bandwidth errors of 7.33\%) while providing substantial speedup (26.8×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, prefetching strategies, memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.

Gajaria, Dhruv Mayur↗
DOE OSTI2026

NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning

Spiking Neural Networks (SNNs) are computational models inspired by the event-driven communication and connectivity patterns of biological neural circuits. They enable high energy efficiency and natural support for diverse architectures ranging from layered networks to small-world and graphstructured topologies. In this work, we introduce NeuroCoreX, an open-source, FPGA-based spiking neural network emulator that provides real-time, on-chip learning and flexible network organization. NeuroCoreX supports both feedforward sensory inputs streamed directly from sensors or PCs via UART and recurrent on-chip connectivity, enabling simultaneous processing and learning from external stimuli and internal network dynamics-capabilities rarely available in existing FPGA SNN platforms. The system implements a Leaky Integrate-and-Fire (LIF) neuron model with current-based synapses and supports pair-based STDP learning on both feedforward and recurrent synapses. A lightweight Python interface enables interactive configuration, live monitoring, weight read-back, and experiment control. Importantly, NeuroCoreX is tightly integrated with the SuperNeuroMAT simulator, allowing SNN models to be transferred seamlessly from software to hardware for hardware-in-the-loop development. By combining real-time plasticity, flexible connectivity, and an open-source VHDL implementation, NeuroCoreX provides an extensible and accessible platform for neuromorphic research, algorithm-hardware co-design, and energy-efficient edge intelligence.

Gautam, Ashish [ORNL]↗
DOE OSTI2026

InterQnet: A Heterogeneous Full-Stack Approach to Co-Designing Scalable Quantum Networks

Quantum communications have progressed significantly, moving from a theoretical concept to small-scale experiments to recent metropolitan-scale demonstrations. As the technology matures, it is expected to revolutionize quantum computing in much the same way that classical networks revolutionized classical computing. Quantum communications will also enable breakthroughs in quantum sensing, metrology, and other areas. However, scalability has emerged as a major challenge, particularly in terms of the number and heterogeneity of nodes, the distances between nodes, the diversity of applications, and the scale of user demand. This article describes InterQnet, a multidisciplinary project that advances scalable quantum communications through a comprehensive approach that improves devices, error handling, and network architecture. InterQnet has a two-pronged strategy to address scalability challenges: InterQnet-Achieve focuses on practical realizations of heterogeneous quantum networks by building and then integrating first-generation quantum repeaters with error mitigation schemes and centralized automated network control systems. The resulting system will enable quantum communications between two heterogeneous quantum platforms through a third type of platform operating as a repeater node. InterQnet-Scale focuses on a systems study of architectural choices for scalable quantum networks by developing forward-looking models of quantum network devices, advanced error correction schemes, and entanglement protocols. Here, we report our current progress toward achieving our scalability goals.

Chung, Joaquin [Argonne] (ORCID:0000000173833810)↗
DOE OSTI2025

SAN-Based Block Polymers as a Platform for Manufacturing Strong Isoporous Membranes

Ultrafiltration (UF) membranes are ubiquitous in water purification and bioprocessing. However, co-designing their mechanical and transport properties remains challenging because of the broad pore size distributions at the surface and within the bulk that result from nonsolvent-induced phase separation (NIPS) – their typical manufacturing process. These distributions influence the hydrodynamic resistance to water flow and the stress concentrations around the pores. Developing advanced UF membranes requires innovative molecular designs that offer control over the surface and bulk pores, as well as the mechanical properties of the load-bearing, polymer. Here, we introduce a platform for designing UF membranes by leveraging solution self-assembly of block polymers and chain architectures with pendant polar groups. The block polymers consist of a poly(styrene-co-acrylonitrile) hydrophobic block, which is known for its strength, and a poly(4-vinyl pyridine) hydrophilic block, which drives solution self-assembly. We focus on a series of block polymers with constant molecular weight, M n ≈ 115 kDa, SAN fraction, 75 wt.%, and varying acrylonitrile content, 0 to 40 mol%, to demonstrate that: (i) RAFT dispersion copolymerization of acrylonitrile and styrene provides a facile route to synthesize strong block polymers, (ii) incorporation of acrylonitrile into the hydrophobic block enhances membrane strength by facilitating chain entanglements and dipole-dipole interactions, and (iii) acrylonitrile alters the balance between membrane permeance and rejection, even when the membranes feature similar surface and bulk pores. Overall, our results provide insights into the molecular design of UF membranes with enhanced mechanical and separation properties, contributing to the development of materials for water and energy technologies.

deformation↗
DOE OSTI2026

Financial-technical co-design for capital-intensive, resource-responsive energy systems

Because of their capital-intensive operation, wind energy systems that are competitive in terms of the cost of the energy that they produce lead to risk-reward trade-offs that make their business cases less favorable than those of conventional energy generation technologies. However, wind energy systems tend to be designed to maximize energy production or minimize cost of energy rather than to maximize their business cases. In this work, we attempt to exploit designs specifically tailored to business cases. We develop a novel framework for analyzing energy systems that ties their design variables to monthly operating incomes using simple models and historical hourly market and resource data. Using this approach, we demonstrate that for a wind site with abundant wind resource in the California Independent System Operator market, we can control the trade-off between mean and 5th percentile monthly returns by choosing the specific power of the turbine at a fixed modeled initial capital cost. Our framework gives a measure of the risk-reward spectrum of energy generation assets that could be built at a given site with respect to the sub-annual resource/market variation.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2025

QUCODE: End-to-End Qubit Co-Design

The design of a quantum computer can be broken down into different steps, e.g., the material science aspect of designing qubits and devices, considerations of controlling the state of the qubits and their environment, the computer science aspects of mapping algorithms to the available primitives of the quantum computer, and the programming of an application in terms of the available algorithms. Research in these areas is currently fairly isolated, and there is framework for an end-to-end design approach where a desired application informs the choice of materials for the qubits and their environment, and vice versa.We identify knowledge gaps and opportunities for research that builds on existing PNNL capabilities.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗