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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Development and Implementation of Non-Newtonian Rheology Into the Generalized Fluid System Simulation Program (GFSSP)

One of the goals of this program was to develop the experimental and analytical/computational tools required to predict the flow of non-Newtonian fluids through the various system components of a propulsion system: pipes, valves, pumps etc. To achieve this goal we selected to augment the capabilities of NASA's Generalized Fluid System Simulation Program (GFSSP) software. GFSSP is a general-purpose computer program designed to calculate steady state and transient pressure and flow distributions in a complex fluid network. While the current version of the GFSSP code is able to handle various systems components the implicit assumption in the code is that the fluids in the system are Newtonian. To extend the capability of the code to non-Newtonian fluids, such as silica gelled fuels and oxidizers, modifications to the momentum equations of the code have been performed. We have successfully implemented in GFSSP flow equations for fluids with power law behavior. The implementation of the power law fluid behavior into the GFSSP code depends on knowledge of the two fluid coefficients, n and K. The determination of these parameters for the silica gels used in this program was performed experimentally. The n and K parameters for silica water gels were determined experimentally at CFDRC's Special Projects Laboratory, with a constant shear rate capillary viscometer. Batches of 8:1 (by weight) water-silica gel were mixed using CFDRC s 10-gallon gelled propellant mixer. Prior to testing the gel was allowed to rest in the rheometer tank for at least twelve hours to ensure that the delicate structure of the gel had sufficient time to reform. During the tests silica gel was pressure fed and discharged through stainless steel pipes ranging from 1", to 36", in length and three diameters; 0.0237", 0.032", and 0.047". The data collected in these tests included pressure at tube entrance and volumetric flowrate. From these data the uncorrected shear rate, shear stress, residence time, and viscosity were evaluated using formulae for non-Newtonian, power law fluids. The maximum shear rates (corrected for entrance effects) obtained in the rheometer with the current setup were in the 150,000 to 170,000sec- range. GFSSP simulations were performed with a flow circuit simulating the capillary rheometer and using Power Law gel viscosity coefficients from the experimental data. The agreement between the experimental data and the simulated flow curves was within +/-4% given quality entrance effect data.

DiSalvo, Roberto↗
NASA NTRS1983

Computer modeling of batteries from non-linear circuit elements

A simple non-linear circuit model for battery behavior is given. It is based on time-dependent features of the well-known PIN change storage diode, whose behavior is described by equations similar to those associated with electrochemical cells. The circuit simulation computer program ADVICE was used to predict non-linear response from a topological description of the battery analog built from advice components. By a reasonable choice of one set of parameters, the circuit accurately simulates a wide spectrum of measured non-linear battery responses to within a few millivolts.

Waaben, S.↗
NASA NTRS2002

Simulation Model of A Ferroelectric Field Effect Transistor

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS1995

Efficient finite element simulation of slot spirals, slot radomes and microwave structures

This progress report contains the following two documents: (1) 'Efficient Finite Element Simulation of Slot Antennas using Prismatic Elements' - A hybrid finite element-boundary integral (FE-BI) simulation technique is discussed to treat narrow slot antennas etched on a planar platform. Specifically, the prismatic elements are used to reduce the redundant sampling rates and ease the mesh generation process. Numerical results for an antenna slot and frequency selective surfaces are presented to demonstrate the validity and capability of the technique; and (2) 'Application and Design Guidelines of the PML Absorber for Finite Element Simulations of Microwave Packages' - The recently introduced perfectly matched layer (PML) uniaxial absorber for frequency domain finite element simulations has several advantages. In this paper we present the application of PML for microwave circuit simulations along with design guidelines to obtain a desired level of absorption. Different feeding techniques are also investigated for improved accuracy.

Gong, J.↗
NASA NTRS1988

Electronic Neural-Network Simulator

Experimental circuits faster than simulation programs run on digital computers. Serial shift register routes clock pulses C1 to neurons in sequence. Clock pulses C2 interrogate neurons. Neuron interconnection information stored in simulated synapses. Can be expanded to greater complexity.

Moopenn, Alex W.↗
NASA NTRS2001

Temperature Effects in Varactors and Multipliers

Varactor diode multipliers are a critical part of many THz measurement systems. The power and efficiencies of these devices limit the available power for THz sources. Varactor operation is determined by the physics of the varactor device and a careful doping profile design is needed to optimize the performance. Higher doped devices are limited by junction breakdown and lower doped structures are limited by current saturation. Higher doped structures typically have higher efficiencies and lower doped structures typically have higher powers at the same operating frequency and impedance level. However, the device material properties are also a function of the operating temperature. Recent experimental evidence has shown that the power output of a multiplier can be improved by cooling the device. We have used a particle Monte Carlo simulation to investigate the temperature dependent velocity vs. electric field in GaAs. This information was then included in a nonlinear device circuit simulator to predict multiplier performance for various temperatures and device designs. This paper will describe the results of this analysis of temperature dependent multiplier operation.

East, J.↗
NASA NTRSDate not supplied

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^8 determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

J Wayne Mullinax↗
NASA NTRSDate not supplied

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^(8) determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

Quantum Computing↗
NASA NTRSDate not supplied

Efficient Implementation for Unitary Coupled Cluster State Preparation for Near-Term Quantum Computers

Unitary coupled cluster theory (UCC) is a common wave function ansatz for quantum simulation of molecular electronic structure using the variational quantum eigenvalue solver (VQE). Even for small molecules using a double-ζ basis, the number of variational parameters required to minimize the electronic energy (i.e., optimize the circuit) is large and beyond the reach of current quantum computers. For example, a circuit simulating C2 using the UCCSD ansatz and the cc-pVDZ basis set with frozen-core will require over 10,000 variational parameters and a Hilbert space of over 10^(8) determinants. To make progress on simulating such molecular systems on near-term quantum computers, we explore how much of the optimization can be approximately prepared with classical simulation while reducing the number of optimization steps performed on a quantum device. Recently, Chen, Cheng, and Freericks [J. Chem. Theory Comput. 2021, 17, 841-847] presented an algorithm for the factorized form of the UCC ansatz that allows for efficient UCC optimizations on classical hardware. We flip the algorithm around and use it to prepare approximate quantum circuits for systems that require a large number of qubits to represent. We will present results from our implementation and discuss strategies for incorporating this implementation for algorithms involving near-term quantum computers.

Quantum Computing↗
NASA NTRS1992

A sweep algorithm for massively parallel simulation of circuit-switched networks

A new massively parallel algorithm is presented for simulating large asymmetric circuit-switched networks, controlled by a randomized-routing policy that includes trunk-reservation. A single instruction multiple data (SIMD) implementation is described, and corresponding experiments on a 16384 processor MasPar parallel computer are reported. A multiple instruction multiple data (MIMD) implementation is also described, and corresponding experiments on an Intel IPSC/860 parallel computer, using 16 processors, are reported. By exploiting parallelism, our algorithm increases the possible execution rate of such complex simulations by as much as an order of magnitude.

Gaujal, Bruno↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗
NASA NTRS1990

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗
NASA NTRS1992

Theoretical and experimental investigation of a rectenna element for microwave power transmission

A microstrip measurement system has been designed to analyze packaged GaAs Schottky barrier diodes under small and large signal conditions. The nonlinear equivalent circuit parameters of the diode are determined using a small signal test method that analyzes the diode's scattering parameters at various bias levels. The experimental results of a 2.45 GHz diode are verified using a nonlinear circuit simulation program based on a multireflection algorithm. A 35 GHz rectenna has been built using a microstrip patch antenna and Ka-band mixer diode. The measured efficiency was 29 percent at 120 mW input power. A frequency selective surface is designed using an equivalent circuit model to reduce the second harmonic radiations for a 2.45 GHz rectenna. Theoretical results are found to be in fairly good agreement with experiments.

Mcspadden, James O.↗
NASA NTRS2012

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin↗
NASA NTRS2011

Lockout/Tagout (LOTO) Simulator

The Lockout/Tagout (LOTO) Simulator is a portable training aid, or demonstration tool, designed to physically illustrate real-time critical-safety concepts of electrical lockout/tagout. The objective is to prevent misinterpretations of what is off and what is on during maintenance and repair of complex electrical systems. The simulator is designed in the form of a hinged box that opens up and stands on its own as an easel for demonstrations. On the outer face of the unit is a simulated circuit breaker box housing the switches. The breakers control the main power to the unit, a light bulb, and an electrical control cabinet. The light bulb is wired so that either of two breakers can provide power to it. When power is sent to the electrical control cabinet, a red indicator light illuminates. Inside the cabinet is the power supply from a personal computer. The power supply produces a 12-V dc output that is sent over to a small fan next to it, also from a computer, and an amber light on the front of the cabinet illuminates. A separate switch powers the fan on and off. The power supply is behind a plastic shield to protect against exposure to live conductors. Electrical banana jacks are mounted in the plastic shield to allow a voltmeter to be connected safely when opening the cabinet and taking a meter reading to verify de-energization as part of a simulation exercise. This LOTO simulator prototype is designed and fabricated as an all-in-one unit. All accessories can be stored inside the hinged case, and there is a handle on top for ease of transport. The circuit breaker labels attach with hook and loop fasteners so that they may be moved and changed to fit the training or demonstration scenario. The warning signs and labels on the electrical control box are magnetic, allowing for easy reconfiguration to emulate different equipment setups. A specially designed magnetic cover was made to disguise the indicator lights for demonstrations when these indicators are not used. The cover is disguised as an arc flash safety label that would typically be found on such a cabinet. One indicator light has a separate switch that can take it offline. This is to allow for demonstration to trainees on why it is important not to completely rely on indicator lights, but that they should always take a meter reading at the exposed conductors to absolutely verify de-energization before exposure. A clear plastic barrier and banana jacks inside the cabinet provide a safe way to plug in a voltmeter for demonstrations without exposure to the hazards of energized equipment. A small remote control unit is wired into the fan circuit. The remote allows the demonstrator to turn the fan on and off, provided that all of the breakers and switches leading to it are configured on as well. The remote feature was added in order to demonstrate the importance of starting the lockout/tagout task with energized equipment, then powering it down, isolating it, and locking it out to ensure that the correct breakers have been locked out.

Scheer, Jennifer↗
NASA NTRS2024

Development of a High Frequency Class-A Amplifier for High Temperature Wireless Microsystems based on a Silicon Carbide Static Induction Transistor

Next generation gas turbine engine health monitoring for high performance jet engine-powered aircraft will incorporate integrated microelectronic sensors specifically designed to enhance aircraft functionality, engine efficiency, and safety. Temperature, air flow and pressure associated with the gas path as well as emissions from the engine correlate to the state of the combustor and other engine health conditions. Monitoring these parameters accurately requires positioning electronic sensors in the hot zone of the gas turbine engine, which exposes them to temperatures in excess of 400ºC. At these temperatures, signal amplification is needed at the transducer level to distinguish the desired measured signal from the significant electronic noise generated by the harsh environment. In this presentation, we report on the simulation, development, fabrication, and testing on a high temperature Class-A amplifier which utilizes a 4H-SiC Static Induction Transistor (SIT) as the active device and input/output matching and DC bias networks comprised of thin-film spiral inductors, metal-insulator-metal capacitors, and thick film chip resistors. A small signal model that emulates the operation of the 4H-SiC SIT from 25 to 400ºC, with an emphasis on operation at 400οC, was utilized. Measurements were performed from 25 to 400ºC to generate current-voltage curves, capacitive transistor characteristics and high frequency scattering parameters (S-parameters). The measured data was used to extrapolate the transconductance, gm, as a function of temperature for model development. Circuit simulation tools were used to generate S-parameters, which were compared to the measured values. At 400οC, a maximum difference between measured and simulated S-parameters for frequencies from 20 to 100 MHz were 3.84%, 0.68%, 10.61%, and 3.26% for S21, S12, S11, and S22, respectively. The average transit frequency, ft, was calculated from measured values to be 197.8 MHz, while the simulated value from the model was found to be 200 MHz. The Amplifier’s S-parameters were recorded at 20-100 MHz over a temperature range of 25-400ºC and show a gain of approximately 15.8 and 5.80 dBm at 25 and 400ºC, respectively. The input and output reflection coefficients at 50 MHz and 400ºC were -18.5 and -15.2 dB, respectively. The noise figure and phase noise were measured over the temperature range of 25-400ºC and recorded. The noise figure increased 21% at 50 MHz over the temperature range, while the 1 kHz offset of the phase noise remained below -110 dB. The stability factor, K, calculated with measured and simulated data demonstrates unconditional stability over the frequency range at 400ºC. Lastly, the 1-dB compression point was measured at 50 MHz and 400ºC with an approximated output of 9.5 dBm.

SiC↗
NASA NTRS1989

Distortion and regulation characterization of a Mapham inverter

Output-voltage total harmonic distortion (THD) of a 20-kHz, 6-kVA Mapham resonant inverter is characterized as a function of its switching-to-resonant frequency ratio, f(s)/f(r), using the EASY5 Engineering Analysis System. EASY5 circuit simulation results are compared with hardware test results to verify the accuracy of the simulations. The effects of load on the THD versus f(s)/f(r) is investigated for resistive, leading, and lagging power factor load impedances. The effect of the series output capacitor on the Mapham inverter output-voltage distortion and inherent load regulation is characterized under loads of various power factors and magnitudes. An optimum series capacitor value which improves the inherent load regulation to better than 3 percent is identified. The optimum series capacitor value is different from the value predicted from a modeled frequency domain analysis. An explanation is proposed which takes into account the conduction overlap in the inductor pairs during steady-state inverter operation, which decreases the effective inductance of a Mapham inverter. A fault protection and current limit method is discussed which allows the Mapham inverter to operate into a short circuit, even when the inverter resonant circuit becomes overdamped.

Sundberg, Richard C.↗