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All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

A Physics of Failure Approach to Evaluate Printed Circuit Board Reliability

Risk based technology infusion is a deliberate and systematic process which defines the analysis and communication methodology by which new technology is applied and integrated into existing and new designs, identifies technology development needs based on trends analysis and facilitates the identification of shortfalls against performance objectives. This presentation at IPC Works Asia Aerospace 2019 Events provides the audience a snapshot of quality variations in printed wiring board quality, as assessed, using experiences in processing and risk analysis of PWB structural integrity coupons. The presentation will focus on printed wiring board quality metrics used, the relative type and number of non-conformances observed and trend analysis using statistical methods. Trend analysis shows the top five non-conformances observed across PWB suppliers, the root cause(s) behind these non-conformance and suggestions of mitigation plans. The trends will then be matched with the current state of the PWB supplier base and its challenges and opportunities. The presentation further discusses the risk based SMA approaches and methods being applied at GSFC for evaluating candidate printed wiring board technologies which promote the adoption of higher throughput and faster processing technology for GSFC missions.

Printed Circuit Boards↗
NASA NTRS2018

Building Reliable Printed Circuit Boards - the Lessons Learned

"Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues."

Sood, Bhanu↗
NASA NTRS1990

The multidriver: A reliable multicast service using the Xpress Transfer Protocol

A reliable multicast facility extends traditional point-to-point virtual circuit reliability to one-to-many communication. Such services can provide more efficient use of network resources, a powerful distributed name binding capability, and reduced latency in multidestination message delivery. These benefits will be especially valuable in real-time environments where reliable multicast can enable new applications and increase the availability and the reliability of data and services. We present a unique multicast service that exploits features in the next-generation, real-time transfer layer protocol, the Xpress Transfer Protocol (XTP). In its reliable mode, the service offers error, flow, and rate-controlled multidestination delivery of arbitrary-sized messages, with provision for the coordination of reliable reverse channels. Performance measurements on a single-segment Proteon ProNET-4 4 Mbps 802.5 token ring with heterogeneous nodes are discussed.

Dempsey, Bert J.↗
NASA NTRS2006

Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

Berg, Melanie↗
NASA NTRS1978

Stable low noise voltage source

Hum and noise on power sources can have a significant effect on system noise. Filtering to achieve low hum and noise is accomplished at low current levels. The diode regulator circuit is described which is ideal for this type of filtering. Hum and noise rejection is achieved with good output voltage stability in a small, low-cost, reliable circuit.

Lutes, G. F.↗
NASA NTRS1990

Reliable VLSI sequential controllers

A VLSI architecture for synchronous sequential controllers is presented that has attractive qualities for producing reliable circuits. In these circuits, one hardware implementation can realize any flow table with a maximum of 2(exp n) internal states and m inputs. Also all design equations are identical. A real time fault detection means is presented along with a strategy for verifying the correctness of the checking hardware. This self check feature can be employed with no increase in hardware. The architecture can be modified to achieve fail safe designs. With no increase in hardware, an adaptable circuit can be realized that allows replacement of faulty transitions with fault free transitions.

Whitaker, S.↗
NASA NTRS1995

High-Voltage MOSFET Switching Circuit

Circuit reliably switches power at supply potential of minus 1,500 V, with controlled frequency and duty cycle. Used in argon-plasma ion-bombardment equipment for texturing copper electrodes, as described in "Texturing Copper To Reduce Secondary Emission of Electrons" (LEW-15898), also adapted to use in powering gaseous flash lamps and stroboscopes.

Jensen, Kenneth A.↗
NASA NTRS2010

26th Space Simulation Conference Proceedings. Environmental Testing: The Path Forward

Topics covered include: A Multifunctional Space Environment Simulation Facility for Accelerated Spacecraft Materials Testing; Exposure of Spacecraft Surface Coatings in a Simulated GEO Radiation Environment; Gravity-Offloading System for Large-Displacement Ground Testing of Spacecraft Mechanisms; Microscopic Shutters Controlled by cRIO in Sounding Rocket; Application of a Physics-Based Stabilization Criterion to Flight System Thermal Testing; Upgrade of a Thermal Vacuum Chamber for 20 Kelvin Operations; A New Approach to Improve the Uniformity of Solar Simulator; A Perfect Space Simulation Storm; A Planetary Environmental Simulator/Test Facility; Collimation Mirror Segment Refurbishment inside ESA s Large Space; Space Simulation of the CBERS 3 and 4 Satellite Thermal Model in the New Brazilian 6x8m Thermal Vacuum Chamber; The Certification of Environmental Chambers for Testing Flight Hardware; Space Systems Environmental Test Facility Database (SSETFD), Website Development Status; Wallops Flight Facility: Current and Future Test Capabilities for Suborbital and Orbital Projects; Force Limited Vibration Testing of JWST NIRSpec Instrument Using Strain Gages; Investigation of Acoustic Field Uniformity in Direct Field Acoustic Testing; Recent Developments in Direct Field Acoustic Testing; Assembly, Integration and Test Centre in Malaysia: Integration between Building Construction Works and Equipment Installation; Complex Ground Support Equipment for Satellite Thermal Vacuum Test; Effect of Charging Electron Exposure on 1064nm Transmission through Bare Sapphire Optics and SiO2 over HfO2 AR-Coated Sapphire Optics; Environmental Testing Activities and Capabilities for Turkish Space Industry; Integrated Circuit Reliability Simulation in Space Environments; Micrometeoroid Impacts and Optical Scatter in Space Environment; Overcoming Unintended Consequences of Ambient Pressure Thermal Cycling Environmental Tests; Performance and Functionality Improvements to Next Generation Thermal Vacuum Control System; Robotic Lunar Lander Development Project: Three-Dimensional Dynamic Stability Testing and Analysis; Thermal Physical Properties of Thermal Coatings for Spacecraft in Wide Range of Environmental Conditions: Experimental and Theoretical Study; Molecular Contamination Generated in Thermal Vacuum Chambers; Preventing Cross Contamination of Hardware in Thermal Vacuum Chambers; Towards Validation of Particulate Transport Code; Updated Trends in Materials' Outgassing Technology; Electrical Power and Data Acquisition Setup for the CBER 3 and 4 Satellite TBT; Method of Obtaining High Resolution Intrinsic Wire Boom Damping Parameters for Multi-Body Dynamics Simulations; and Thermal Vacuum Testing with Scalable Software Developed In-House.

Packard, Edward A.↗