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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1973

Design and flight performance evaluation of the Mariners 6, 7, and 9 short-circuit current, open-circuit voltage transducers

The purpose of the short-circuit voltage transducer is to provide engineering data to aid the evaluation of array performance during flight. The design, fabrication, calibration, and in-flight performance of the transducers onboard the Mariner 6, 7 and 9 spacecrafts are described. No significant differences were observed in the in-flight electrical performance of the three transducers. The transducers did experience significant losses due to coverslides or adhesive darkening, increased surface reflection, or spectral shifts within coverslide assembly. Mariner 6, 7 and 9 transducers showed non-cell current degradations of 3-1/2%, 3%, and 4%, respectively at Mars encounter and 6%, 3%, and 4-12%, respectively at end of mission. Mariner 9 solar Array Test 2 showed 3-12% current degradation while the transducer showed 4-12% degradation.

Patterson, R. E.↗
NASA NTRS1973

Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

Source record↗
NASA NTRS1995

Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits

A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

Buehler, Martin G.↗
NASA NTRS2006

Submicrosecond Power-Switching Test Circuit

A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a repetitive waveform from a signal generator, momentary closure of a push-button switch, or closure or opening of a manually operated on/off switch. In the case of a signal generator, one can adjust the frequency and duty cycle as needed to obtain the desired AC power-supply response, which one could display on an oscilloscope. Momentary switch closure could be useful for obtaining (and, if desired, displaying on an oscilloscope set to trigger on an event) the response of a power supply to a single load transient. The on/off switch can be used to switch between load states in which static-load regulation measurements are performed.

Folk, Eric N.↗
NASA NTRS2022

Space Induced Discharge Model to Be Used on Interface Circuit Vulnerability Assessment

Charging can occur in space due to plasma and high energy particles. Charging is especially severe in certain earth orbits such as geostationary orbit, medium earth orbit and highly inclined orbit. A spacecraft that travels to other planets such as Jupiter also encounters high level of charging due to Jupiter’s radiation belt. The major concern for spacecraft operation due to charging is the survival of sensitive electrical circuits. Dielectrics and floating metal can charge up and discharge onto interface circuits. The electrical circuits need to be evaluated for survival from the electrostatic-discharge (ESD) threat. Both ESD induced upset and damage need to be assessed. The interface circuits are often located inside a shielded unit in the spacecraft structure or a shielded vault with sufficient radiation shielding to avoid surface and internal charging. The materials external to the highly shielded area can charge up and discharge onto wires that can directly dissipate the ESD onto the interface circuits. Figure 1 shows a possible discharge mechanism onto the interfacing circuits. If the wire has an external shield or a coaxial line, some or most of the discharge can flow on the shield to chassis ground. There is always coupling from external discharge. If the wire has no shield, the discharge flows onto the interface circuit. Fig. 1 Possible discharge paths onto the interface circuits. The purpose of this article is to address how to model the ESD threat to be used as the discharge source onto the interface circuit based on the electron beam test data. Different models are needed for different impedances associated with the interface circuits. Once those models are derived, one needs to analyze the interface circuit with the corresponding model using an electrical simulation tool. Then, the circuit’s front-end components can be assessed for damage and upset. Upset is highly dependent on the circuit operation and system requirements, and thus it is not addressed any further. Damage of electrical parts is often rated under Human-Body-Model (HBM) ESD. One can utilize this industry-wide available information to assess the damage vulnerability due to space discharges. However, the HBM waveform does not always match the discharge waveform. To estimate the damage vulnerability of the circuit and set margin, one needs to compare the equivalent energy delivered to the victim between a HBM discharge and the results from an ESD source model based on actual discharges. This paper presents such a comparison for a few select cases.

Xie, Julie↗
NASA NTRS1973

Phase control circuits using frequency multiplications for phased array antennas

A phase control coupling circuit for use with a phased array antenna is described. The coupling circuit includes a combining circuit which is coupled to a transmission line, a frequency multiplier circuit which is coupled to the combining circuit, and a recombining circuit which is coupled between the frequency multiplier circuit and phased array antenna elements. In a doubler embodiment, the frequency multiplier circuit comprises frequency doublers and the combining and recombining circuits comprise four-port hybrid power dividers. In a generalized embodiment, the multiplier circuit comprises frequency multiplier elements which multiply to the Nth power, the combining circuit comprises four-part hybrid power dividers, and the recombinding circuit comprises summing circuits.

Mailloux, R. J.↗
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS1994

Novel high-gain, improved-bandwidth, finned-ladder V-band Traveling-Wave Tube slow-wave circuit design

The V-band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for inter-satellite communications. As a first effort to develop a high-efficiency V-band Traveling-Wave Tube (TWT), variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite these advantages, however, low bandwidth and high voltage requirements have, until now, prevented its acceptance outside the laboratory. In this paper, the three-dimensional electrodynamic simulation code MAFIA (solution of MAxwell's Equation by the Finite-Integration-Algorithm) is used to investigate methods of increasing the bandwidth and lowering the operating voltage of the ring-plane circuit. Calculations of frequency-phase dispersion, beam on-axis interaction impedance, attenuation and small-signal gain per wavelength were performed for various geometric variations and loading distributions of the ring-plane TWT slow-wave circuit. Based on the results of the variations, a circuit termed the finned-ladder TWT slow-wave circuit was designed and is compared here to the scaled prototype ring-plane and a conventional ferruled coupled-cavity TWT circuit over the V-band frequency range. The simulation results indicate that this circuit has a much higher gain, significantly wider bandwidth, and a much lower voltage requirement than the scaled ring-plane prototype circuit, while retaining its excellent thermal dissipation properties. The finned-ladder circuit has a much larger small-signal gain per wavelength than the ferruled coupled-cavity circuit, but with a moderate sacrifice in bandwidth.

Kory, Carol L.↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗
NASA NTRS2005

Faster Evolution of More Multifunctional Logic Circuits

A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.

Stoica, Adrian↗