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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip

The ITkPixV2 chip is the final production readout chip for the ATLAS Phase 2 Inner Tracker (ITk) upgrade at the upcoming High-Luminosity LHC (HL-LHC). Due to the extraordinarily high peak luminosity at the HL-LHC of 5 × 1034 cm-1 s-1, ITkPixV2 must meet significant increases in nearly all design requirements compared to the current ATLAS Inner Detector (ID), including a 10× increase in trigger rate, a 7.5× increase in hit rate, a 3× increase in radiation tolerance, and a 12.5× decrease in pixel current draw per unit area, all while maintaining a similar power per unit area as present pixel detectors. Here we present the first measurements of the ITkPixV2 chip operated at the limits of the full chip design requirements, including in particular a measurement of the activity-induced current of the chip as a function of increasing hit rate.

Le Pottier, L↗
DOE OSTI2025

Simultaneous on-chip generation of violet, blue, cyan, green, yellow, orange, and red light from an octave-spanning infrared frequency comb

An integrated, multi-spectral visible-light source could significantly benefit technologies such as displays, medical imaging, spectroscopy, visible-light communications, and astrophysics. However, despite recent advances in chip-scale visible lasers, simultaneously generating light of all colors in a single chip has been challenging. Existing solutions are either not suitable for full chip-scale integration, or are fundamentally difficult to scale. Here we demonstrate the simultaneous on-chip generation of infrared, red, orange, yellow, green, cyan, blue, and violet light. Leveraging the low loss, low dispersion, and high density of modes of an adiabatic multimode silicon nitride (SiN) microresonator, we use a single infrared pump of moderate power (~130 mW) to produce an octave-spanning infrared frequency comb that is then converted to different portions of the visible spectrum. We measure non-mode-locked combs and soliton steps corresponding to mode-locked states, making our comb generator suitable for applications that demand either low or high coherence. Since the required pump power is compatible with high-power lasers demonstrated in the same SiN platform, our multi-octave light generator can be fully integrated in a chip-scale form factor. We envision that such a light source will be a catalyst for the development and deployment of miniaturized multi-spectral technologies for quantum systems, medical imaging, displays, and spectroscopy.

47 OTHER INSTRUMENTATION↗
NASA NTRS1991

A very high speed lossless compression/decompression chip set

A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.

Venbrux, Jack↗
NASA NTRS2004

A Low Cost Single Chip VDL Compatible Transceiver ASIC

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Becker, Robert↗
NASA NTRS2009

Manipulating Neutral Atoms in Chip-Based Magnetic Traps

Several techniques for manipulating neutral atoms (more precisely, ultracold clouds of neutral atoms) in chip-based magnetic traps and atomic waveguides have been demonstrated. Such traps and waveguides are promising components of future quantum sensors that would offer sensitivities much greater than those of conventional sensors. Potential applications include gyroscopy and basic research in physical phenomena that involve gravitational and/or electromagnetic fields. The developed techniques make it possible to control atoms with greater versatility and dexterity than were previously possible and, hence, can be expected to contribute to the value of chip-based magnetic traps and atomic waveguides. The basic principle of these techniques is to control gradient magnetic fields with suitable timing so as to alter a trap to exert position-, velocity-, and/or time-dependent forces on atoms in the trap to obtain desired effects. The trap magnetic fields are generated by controlled electric currents flowing in both macroscopic off-chip electromagnet coils and microscopic wires on the surface of the chip. The methods are best explained in terms of examples. Rather than simply allowing atoms to expand freely into an atomic waveguide, one can give them a controllable push by switching on an externally generated or a chip-based gradient magnetic field. This push can increase the speed of the atoms, typically from about 5 to about 20 cm/s. Applying a non-linear magnetic-field gradient exerts different forces on atoms in different positions a phenomenon that one can exploit by introducing a delay between releasing atoms into the waveguide and turning on the magnetic field.

Aveline, David↗
NASA NTRS2012

Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

Park, Yeonjoon↗
NASA NTRS2015

Towards a Generic and Adaptive System-On-Chip Controller for Space Exploration Instrumentation

This paper introduces one of the first efforts conducted at NASA’s Jet Propulsion Laboratory (JPL) to develop a generic System-on-Chip (SoC) platform to control science instruments that are proposed for future NASA missions. The SoC platform is named APEX-SoC, where APEX stands for Advanced Processor for space Exploration, and is based on a hybrid Xilinx Zynq that combines an FPGA and an ARM Cortex-A9 dual-core processor on a single chip. The Zynq implements a generic and customizable on-chip infrastructure that can be reused with a variety of instruments, and it has been coupled with a set of off-chip components that are necessary to deal with the different instruments. We have taken JPL’s Compositional InfraRed Imaging Spectrometer (CIRIS), which is proposed for NASA icy moons missions, as a use-case scenario to demonstrate that the entire data processing, control and interface of an instrument can be implemented on a single device using the on-chip infrastructure described in this paper. We show that the performance results achieved in this preliminary version of the instrumentation controller are sufficient to fulfill the science requirements demanded to the CIRIS instrument in future NASA missions, such as Europa.

embedded system↗
NASA NTRS2018

NEPP Evaluation of Automotive Grade Tantalum Chip Capacitors

Automotive grade tantalum (Ta) chip capacitors are available at lower cost with smaller physical size and higher volumetric efficiency compared to military/space grade capacitors. Designers of high reliability aerospace and military systems would like to take advantage of these attributes while maintaining the high standards for long-term reliable operation they are accustomed to when selecting military-qualified established reliability tantalum chip capacitors (e.g., MIL-PRF-55365). The objective for this evaluation was to assess the long-term performance of off-the-shelf automotive grade Ta chip capacitors (i.e., manufacturer self-qualified per AEC Q-200). Two (2) lots of case size D manganese dioxide (MnO2) cathode Ta chip capacitors from 1 manufacturer were evaluated. The evaluation consisted of construction analysis, basic electrical parameter characterization, extended long-term (2000 hours) life testing and some accelerated stress testing. Tests and acceptance criteria were based upon manufacturer datasheets and the Automotive Electronics Council's AEC Q-200 qualification specification for passive electronic components. As-received a few capacitors were marginally above the specified tolerance for capacitance and ESR. X-ray inspection found that the anodes for some devices may not be properly aligned within the molded encapsulation leaving less than 1 mil thickness of the encapsulation. This evaluation found that the long-term life performance of automotive grade Ta chip capacitors is generally within specification limits suggesting these capacitors may be suitable for some space applications.

Automotive↗
NASA NTRSDate not supplied

Testing of the ISS’s Charcoal HEPA Integrated Particle Scrubber (CHIPS) Filters to Ascertain an Efficiency Curve and Most Penetrating Particle Size

High air quality is a top priority in hermetically sealed environments, such as the International Space Station (ISS). Aerosol particulate filtration on the ISS is achieved via 21 HEPA filters. Traditional HEPA filters have an efficiency of 99.97%, but HEPA filters aboard the ISS have been found to achieve 99.99% efficiency. This may be due to the flight-grade HEPA filters chosen or, less likely, that they are combined with activated charcoal filters for siloxane removal in a combination referred to as Charcoal HEPA Integrated Particle Scrubbers (CHIPS) filters. All filters have a Most Penetrating Particle Size (MPPS), but, until now, the MPPS and efficiency curve of the CHIPS filters was not known. The efficiency curve of the CHIPS filters was ascertained at NASA Glenn Research Center through standard salt crystal aerosolization. This method was selected over aerosolized oil droplets due to a desire to preserve the filter’s function for further testing. The CHIPS filters were tested as they are oriented on the ISS (activated charcoal filter followed by a flight-grade HEPA filter), with the HEPA portion alone, and with the activated charcoal portion alone. The results of this experiment are generally useful but can be especially useful for the microbiology and Environmental Control and Life Support Systems (ECLSS). This is due to microbial contamination being a potential concern in the air revitalization systems on the ISS. Knowing the MMPS of the CHIPS filters, in conjunction with levels of airborne microbes, is useful for predicting which and how many microbes are likely to get through the HEPA filters that sit in the beginning of the ISS airstream. It may also be useful to other groups at NASA to know how many particulates are able to pass through high-efficiency filtration, and even for healthcare cleanrooms and other air purification pursuits.

A Nicolas Whitlock↗
DOE OSTI2025

Simulating Alpha Particles Incident on MKID Chips for Quantum Sensitivity Analysis

Superconducting quantum devices, such as microwave kinetic inductance detectors (MKIDs), are highly sensitive instruments used in quantum computing and advanced sensing technologies. However, their extreme sensitivity also makes them vulnerable to background noise from natural sources like radiation. One significant contributor to this noise is alpha particles emitted by 210Po, a radon decay daughter that accumulates on surfaces near the detector. This project investigates how alpha particles emitted from 210Po interact with MKID chips. These particles can deposit energy on the detector surface, disrupting its operation and generating false signals. Understanding the energy and behavior of these particles is crucial for improving the design and reliability of quantum devices. To explore this, we first modeled the decay chain starting from 210Pb to 210Po using differential equations. This allowed us to predict how the activity of alpha-emitting isotopes changes over time, reaching a steady state after about two years. Next, we simulated alpha particle interactions with the MKID chip using the Geant4 software toolkit. We built a detailed computer model of the detector housing, including the copper lid where alpha particles originate, the silicon chip, and a thin aluminum sensor layer. Alpha particles were emitted isotropically from just beneath the copper lid’s surface, mimicking natural decay conditions. The simulation tracked how these particles deposit energy on the chip, generating electron-hole pairs and phonons. The results provide insight into the behavior of the resultant electron-hole pairs and phonons, giving us a clear understanding of the energy deposition distribution on the chip. This work supports efforts to mitigate background noise in superconducting sensors, advancing their use in quantum computing and sensitive physics experiments.

Hall, Matthew [Fermilab; UCLA]↗
NASA NTRS2004

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

power switch slice (PSS)↗
DOE OSTI2025

An on-chip phased array for non-classical light

Abstract Quantum science and technology can offer fundamental enhancements in sensing, communications and computing. The expansion from wired to wireless links is an exciting prospect for quantum technologies. For classical technologies, the advent of phased arrays enabled directional and adaptive wireless links by manipulating electromagnetic waves over free space. Here we demonstrate a phased array system on a chip that can receive, image and manipulate non-classical light over free space. We use an integrated photonic-electronic system with more than 1000 functional components on-chip to detect squeezed light. By integrating an array of 32 sub-wavelength engineered metamaterial antennas, we demonstrate a direct free-space-to-chip interface for reconfigurable quantum links. On the same chip, we implement a large-scale array of quantum-limited coherent receivers that can resolve non-classical signals simultaneously across 32 channels. With coherent readout and manipulation of these signals, we demonstrate 32-pixel imaging and spatially configurable reception of squeezed light over free space. Our work advances wireless quantum technologies that could enable practical applications in quantum communications and sensing.

Science & Technology - Other Topics↗
NASA NTRS1982

Exit chipping in ID sawing of silicon crystals

The processes involved in exit chipping which may occur in the internal diameter diamond sawing of silicon crystals were examined. An interpretation of chipping observations is given in terms of crack propagation as acted upon by the sawing stresses. Since the exit chips are roughly parallel to saw marks, the general locus of the crack must be determined by contact stresses although the exact locus depends on already existing subfractures located in the kerf region which are caused by more than one abrasive particle. The crack starts at either edge since these are weak areas in flexure. In the more extensive "saw fracture", the fracture plane often changes part-way across the slice to be other than parallel to the saw mark because the speed of the crack accelerates beyond the speed of the blade travel; i.e., outstrips the advance of the contact stress field. The influences of various external factors on the opening of the crack are divided into two types: factors that wedge the crack apart and those that bend the slice away from the crystal. From a consideration of these factors, conditions for minimizing exit chipping are defined.

Dyer, L. D.↗
NASA NTRS1982

Planar multijunction high voltage solar cell chip

A new innovative planar multijunction solar cell chip for concentrated sunlight applications is proposed. The chip consists of many voltage-generating regions, called unit cells, which are connected in series within a single silicon wafer, thereby providing a high open-circuit voltage at multiple sun illumination levels. The unit cells are fabricated on 75 micron thick p-type single crystal silicon substrate. Each chip consists of 1.42 x 9.63 mm n(+)/p collecting junctions on the back of the wafer, while the illuminated front surface area is divided into 0.3 micron deep n(+) regions. The fabrication sequence includes standard degreasing and cleaning procedures, double-sided alignment photomasking, introduction of boron and phosphorus impurities, and photolithography. The open circuit voltage of the chip increased rapidly with illumination up to about 4 AM1 suns, and then began to saturate at the sum of the individual unit cell voltages of 3.5 above 4 AM1 suns. A short circuit density per unit cell of 300 mA/sq cm at 20 AM1 suns was observed.

Valco, G. J.↗
NASA NTRS1984

Chip level modeling of LSI devices

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Armstrong, J. R.↗
NASA NTRS1987

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗
NASA NTRS1986

A system for the functional testing and simulation of custom and semicustom VLSI chips

A system for the functional testing and simulation of custom and semicustom very large scale integrated (VLSI) chips that are designed using the integrated UNIX-based computer-aided design (CAD) system is described. The testing and simulation system consists of two parts. One of these is a special purpose hardware device that is capable of controlling the digital imputs and outputs on a custom chip. This device, the Digital Microcircuit Functionality Tester (DMFT) system, can be operated by itself or in conjunction with the VAX host computer on the CAD system. The DMFT is integrated into a microprobe station so that these signals can be injected or read from nodes inside the chip, as well as at the pins. The second part of the system is a software package that is installed on the VAX. This software package, logic, includes a full-screen editor for developing chip test sequences and drivers for both the DMFT and the esim logic simulator.

Olson, E. M.↗
NASA NTRS1989

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.↗