Performance of self bit synchronization systems
Optimum estimator for random signal sequence derived by digital computer and evaluated by Monte Carlo method
Luecke, E. J.↗
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Results for “BIT SYNCHRONIZATION”
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An adaptive estimation algorithm for time-varying bit synchronizers.
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Chow, L. R.↗
A hybrid general-purpose bit synchronizer
Synchronizer is not affected by severe noise environments. Device uses both analog and digital techniques in its tracking loop. It accommodates any one of three signal formats. Rapid acquisition sequences are used to minimize acquisition time.
Stiffler, J. J.↗
Hardware simulation of Ku-band spacecraft receiver and bit synchronizer, volume 1
A hardware simulation which emulates an automatically acquiring transmit receive spread spectrum communication and tracking system and developed for use in future NASA programs involving digital communications is considered. The system architecture and tradeoff analysis that led to the selection of the system to be simulated is presented.
Lindsey, W. C.↗
Hardware simulation of KU-band spacecraft receiver and bit synchronizer, phase 2, volume 1
The acquisition behavior of the PN subsystem of an automatically acquiring spacecraft receiver was studied. A symbol synchronizer subsystem was constructed and integrated into the composite simulation of the receiver. The overall performance of the receiver when subjected to anomalies such as signal fades was evaluated. Potential problems associated with PN/carrier sweep interactions were investigated.
Lindsey, W. C.↗
Bit-synchronizer lock detector
Circuit measures phase error that exists in phase-locked loop between clock signal recorded in data on magnetic tape and reconstructed clock signal. Circuit presents error as digital word that can be compared with predetermined threshold to indicate lock status. With simple alterations, circuit can also be used as phase detector.
Huey, D. C.↗
Shuttle bit rate synchronizer
A shuttle bit rate synchronizer brassboard unit was designed, fabricated, and tested, which meets or exceeds the contractual specifications. The bit rate synchronizer operates at signal-to-noise ratios (in a bit rate bandwidth) down to -5 dB while exhibiting less than 0.6 dB bit error rate degradation. The mean acquisition time was measured to be less than 2 seconds. The synchronizer is designed around a digital data transition tracking loop whose phase and data detectors are integrate-and-dump filters matched to the Manchester encoded bits specified. It meets the reliability (no adjustments or tweaking) and versatility (multiple bit rates) of the shuttle S-band communication system through an implementation which is all digital after the initial stage of analog AGC and A/D conversion.
Huey, D. C.↗
Critique of a Hughes shuttle Ku-band data sampler/bit synchronizer
An alternative bit synchronizer proposed for shuttle was analyzed in a noise-free environment by considering the basic operation of the loop via timing diagrams and by linearizing the bit synchronizer as an equivalent, continuous, phased-lock loop (PLL). The loop is composed of a high-frequency phase-frequency detector which is capable of detecting both phase and frequency errors and is used to track the clock, and a bit transition detector which attempts to track the transitions of the data bits. It was determined that the basic approach was a good design which, with proper implementation of the accumulator, up/down counter and logic should provide accurate mid-bit sampling with symmetric bits. However, when bit asymmetry occurs, the bit synchronizer can lock up with a large timing error, yet be quasi-stable (timing will not change unless the clock and bit sequence drift). This will result in incorrectly detecting some bits.
Holmes, J. K.↗
Synchronization and bit timing.
Self synchronization and bit timing in detection of digital signals
Wintz, P. A.↗
Pulse code modulated signal synchronizer
A bit synchronizer for a split phase PCM transmission is reported that includes three loop circuits which receive incoming phase coded PCM signals. In the first loop, called a Q-loop, a generated, phase coded, PCM signal is multiplied with the incoming signals, and the frequency and phase of the generated signal are nulled to that of the incoming subcarrier signal. In the second loop, called a B-loop, a circuit multiplies a generated signal with incoming signals to null the phase of the generated signal in a bit phase locked relationship to the incoming signal. In a third loop, called the I-loop, a phase coded PCM signal is multiplied with the incoming signals for decoding the bit information from the PCM signal. A counter means is used for timing of the generated signals and timing of sample intervals for each bit period.
Kobayashi, H. S.↗
Modulation and synchronization technique for MF-TDMA system
This report addresses modulation and synchronization techniques for a multi-frequency time division multiple access (MF-TDMA) system with onboard baseband processing. The types of synchronization techniques analyzed are asynchronous (conventional) TDMA, preambleless asynchronous TDMA, bit synchronous timing with a preamble, and preambleless bit synchronous timing. Among these alternatives, preambleless bit synchronous timing simplifies onboard multicarrier demultiplexer/demodulator designs (about 2:1 reduction in mass and power), requires smaller onboard buffers (10:1 to approximately 3:1 reduction in size), and provides better frame efficiency as well as lower onboard processing delay. Analysis and computer simulation illustrate that this technique can support a bit rate of up to 10 Mbit/s (or higher) with proper selection of design parameters. High bit rate transmission may require Doppler compensation and multiple phase error measurements. The recommended modulation technique for bit synchronous timing is coherent QPSK with differential encoding for the uplink and coherent QPSK for the downlink.
Faris, Faris↗
120 MB/S and 240 MB/S bit synchronizer-signal conditioners for NASA high data rate applications
Two bit synchronizer-signal conditioners (BSSC) developed for NASA high data rate applications such as earth resources monitoring are described. One BSSC is centered at 120 MB/s and the other at 240 Mb/s. These subsystems are featured out of the total hardware developed because the BSSC is such a key subsystem in determining overall system statistical performance. These units represent an evolution of high data rate BSSC's available at low data rates. Numerous inputs/outputs, control functions, indicators, plus the ability to minimize the effects of various signal perturbations are provided. Examples of allowed perturbations are input level variations, bit rate variance static and dynamic, baseline, transition density, bandlimiting, etc., as well as noise. Emphasis in the past has been primarily concerned only with noise.
Gray, J. S.↗
Digital signal processor and processing method for GPS receivers
A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.
Thomas, Jr., Jess B.↗
The effects of transmitter/receiver clock time-base instability on coherent communication system performance
The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit-error probability. The types of time-base instability modeled and analyzed include what is commonly referred to as bit jitter (epoch jitter), bit-jitter rate (time interval jitter), and data asymmetry. The bit-error probability is determined as a function of the statistical characteristics of the time-base instability, the data-transition density, the signal-to-noise ratio in the bit-rate bandwidth and the mechanizations of both the data-bit detector and bit synchronizer. The latter is manifested through the bit synchronizer's natural frequency and loop-damping parameters. Numerical results which indicate the sensitivity of the system bit-error rate to various parameters of the model are provided.
Chie, C. M.↗
Maximum likelihood synchronizer for binary overlapping PCM/NRZ signals.
A maximum likelihood parameter estimation technique for the self bit synchronization problem is investigated. The input sequence to the bit synchronizer is a sequence of binary overlapping PCM/NRZ signal in the presence of white Gaussian noise with zero mean and known variance. The resulting synchronizer consists of matched filters, a transition device and a weighting function. Finally, the performance is examined by Monte Carlo simulations.
Wang, C. D.↗
Precious bits: frame synchronization in Jet Propulsion Laboratory's Advanced Multi-Mission Operations System (AMMOS)
The Jet Propulsion Laboratory's (JPL) Advanced Multi-Mission Operations System (AMMOS) system processes data received from deep-space spacecraft, where error rates are high, bit rates are low, and every bit is precious. Frame synchronization and data extraction as performed by AMMOS enhanced data acquisition and reliability for maximum data return and validity.
code↗
Performance of optimum and suboptimum synchronizers.
Optimum and suboptimum synchronizers for extracting bit synchronization from binary data, showing performance dependence on pertinent system parameters
Luecke, E. J.↗
An all-digital Manchester symbol synchronizer for Space Shuttle
The Shuttle S-Band relay communications links via TDRS are coded and may operate at symbol signal-to-noise ratios (Es/No) as low as -5dB. A brass-board all-digital bit synchronizer with very low (0.05dB) degradation relative to an idealized analog model has been designed to process the 216 KBPS Manchester data symbols. This all-digital bit synchronizer, which provides soft decision detected outputs to a convolutional decoder, may be operated at any rate below 216 KBPS by merely changing the master clock frequency.
Batson, B. H.↗