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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2

Application of Thermo-Mechanical Measurements of Plastic Packages for Reliability Evaluation of PEMS

Thermo-mechanical analysis (TMA) is typically employed for measurements of the glass transition temperature (Tg) and coefficients of thermal expansion (CTE) in molding compounds used in plastic encapsulated microcircuits (PEMs). Application of TMA measurements directly to PEMs allows anomalies to be revealed in deformation of packages with temperature, and thus indicates possible reliability concerns related to thermo-mechanical integrity and stability of the devices. In this work, temperature dependencies of package deformation were measured in several types of PEMs that failed environmental stress testing including temperature cycling, highly accelerated stress testing (HAST) in humid environments, and bum-in (BI) testing. Comparison of thermo-mechanical characteristics of packages and molding compounds in the failed parts allowed for explanation of the observed failures. The results indicate that TMA of plastic packages might be used for quality evaluation of PEMs intended for high-reliability applications.

Sharma, Ashok K.↗

Engineering Area Investigation of Reliability Attributes and Accelerated Stress Factors on Terrestrial Solar Cells

Results obtained include the definition of a simplified stress test schedule for terrestrial solar cells based on the work performed during the first program year, and the design and fabrication of improved jigs and fixtures for electrical measurement and stress testing. Implementation of these advanced techniques for accelerated stress testing is underway on three solar cell types. In addition, review of the literature on second quadrant phenomena was begun and some preliminary second-quadrant electrical measurements were performed. Results obtained at the first down time for 75 C B-T testing and biased and unbiased T-H pressure cooker testing of type F cells showed little or no degradation in electrical parameters. Significant physical effects (large solder bubbles) were noted for type F cells subjected to the pressure cooker stress test.

Lathrop, J. W.↗

NEPP Evaluation of Automotive Grade Tantalum Chip Capacitors

Automotive grade tantalum (Ta) chip capacitors are available at lower cost with smaller physical size and higher volumetric efficiency compared to military/space grade capacitors. Designers of high reliability aerospace and military systems would like to take advantage of these attributes while maintaining the high standards for long-term reliable operation they are accustomed to when selecting military-qualified established reliability tantalum chip capacitors (e.g., MIL-PRF-55365). The objective for this evaluation was to assess the long-term performance of off-the-shelf automotive grade Ta chip capacitors (i.e., manufacturer self-qualified per AEC Q-200). Two (2) lots of case size D manganese dioxide (MnO2) cathode Ta chip capacitors from 1 manufacturer were evaluated. The evaluation consisted of construction analysis, basic electrical parameter characterization, extended long-term (2000 hours) life testing and some accelerated stress testing. Tests and acceptance criteria were based upon manufacturer datasheets and the Automotive Electronics Council's AEC Q-200 qualification specification for passive electronic components. As-received a few capacitors were marginally above the specified tolerance for capacitance and ESR. X-ray inspection found that the anodes for some devices may not be properly aligned within the molded encapsulation leaving less than 1 mil thickness of the encapsulation. This evaluation found that the long-term life performance of automotive grade Ta chip capacitors is generally within specification limits suggesting these capacitors may be suitable for some space applications.

Automotive↗

Investigation of reliability attributes and accelerated stress factors on terrestrial solar cells

Three tasks were undertaken to investigate reliability attributes of terrestrial solar cells: (1) a study of the electrical behavior of cells in the second (reverse) quadrant; (2) the accelerated stress testing of three new state-of-the-art cells; and (3) the continued bias-temperature testing of four block 2 type silicon cells at 78 C and 135 C. Electrical characteristics measured in the second quadrant were determined to be a function of the cell's thermal behavior with breakdown depending on the initiation of localized heating. This implied that high breakdown cells may be more fault tolerant when forced to operate in the second quadrant, a result contrary to conventional thinking. The accelerated stress tests used in the first (power) quadrant were bias-temperature, bias-temperature-humidity, temperature-humidity, thermal shock, and thermal cycle. The new type cells measured included an EFG cell, a polycrystalline cell, and a Czochralski cell. Significant differences in the response to the various tests were observed between cell types. A microprocessed controlled, short interval solar cell tester was designed and construction initiated on a prototype.

Lathrop, J. W.↗

Contact integrity testing of stress-tested silicon terrestrial solar cells

A test procedure was developed and applied to terrestrial silicon solar cells in order to determine the effect of accelerated environmental and time-temperature aging on metal contact integrity. Quantities of cells of four different manufacturers were given the contact integrity test after being subjected to accelerated stress tests that included forward bias-temperature, thermal cycle and thermal shock, power cycle, and bias-temperature humidity tests at two temperature-humidity levels. Significant effects due to certain stress tests were found for some cell types. It is concluded that cells fabricated using plated nickel/solder metallization showed significantly more serious contact integrity degradation than silver-metallized cells.

Prince, J. L.↗

Outdoor performance testing of thin-film devices

The Advanced Systems Research Group supports the photovoltaic advanced R&D (PV AR&D) project by providing outdoor (global) testing of PV cells, submodules, modules, and arrays. The group also provides in house engineering and analysis to identify and determine how technical issues such as cell/module/system adaptations, long term stability, reliability, economics, materials availability, safety, and environmental impacts affect the development and ultimate use of advanced PV thin film, innovative cell, and material technologies. A major thrust of the research effort is to develop and utilize instrumentation and procedures for monitoring and analyzing PV cells and submodules including outdoor performance and stability testing and life cycle accelerated stress testing. To accomplish the above, the solar energy research institute (SERI) outdoor PV test facility was established in 1982. The group has designed testing systems and analysis procedures for, and has tested, numerous amorphous silicon thin film submodules provided by SERI subcontractors and has performed long term outdoor stability tests on CdS/CuIr Se sub 2 and hydrogen passivated silicon solar cells. A significant contribution from this facility over the past year was the testing of large area amorphous silicon submodules.

Source record↗

Nondestructive Evaluation and Monitoring Results from COPV Accelerated Stress Rupture Testing, NASA White Sands Test Facility (WSTF)

Develop and demonstrate NDE techniques for real-time characterization of CPVs and, where possible, identification of NDE capable of assessing stress rupture related strength degradation and/or making vessel life predictions (structural health monitoring or periodic inspection modes). Secondary: Provide the COPV user and materials community with quality carbon/epoxy (C/Ep) COPV stress rupture progression rate data. Aid in modeling, manufacturing, and application of COPVs for NASA spacecraft.

Saulsberry Regor↗

Solar cell reliability testing

The progress and initial data on accelerated stress tests on small amorphous silicon test samples from several manufacturers are reported. The test samples include both single and tandem junction devices.

Lathrop, J.↗

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗

Observed changes in a-Si:H cell characteristics due to long term temperature stress

Determination of thermally induced degradation mechanisms affecting thin film amorphous silicon solar cells through the use of laboratory accelerated stress testing requires acquisition of specially constructed, individually addressable test cells and the development of highly repeatable instrumentation which is not influenced by short-term reversible optical effects. This paper illustrates these considerations by describing accelerated temperature stress procedures and test results for one type of a-Si:H cell. Observed electrical characteristic changes indicate that two types of stress induced mechanisms are operating - one of which is self limiting and can be observed at lower temperatures and one which continues to complete degradation. The self limiting mechanism can result in a dramatic improvement to cells having initially low Voc values.

Lathrop, Jay W.↗

Accelerated degradation of silicon metallization systems

Clemson University has been engaged for the past five years in a program to determine the reliability attributes of solar cells by means of accelerated test procedures. The cells are electrically measured and visually inspected and then subjected for a period of time to stress in excess of that normally encountered in use, and then they are reinspected. Changes are noted and the process repeated. This testing has thus far involved 23 different unencapsulated cell types from 12 different manufacturers, and 10 different encapsulated cell types from 9 different manufacturers. Reliability attributes of metallization systems can be classified as major or minor, depending on the severity of the effects observed. As a result of the accelerated testing conducted under the Clemson program, major effects have been observed related to contact resistance and to mechanical adherence and solderability. This paper does not attempt a generalized survey of accelerated test results, but rather concentrates on one particular attribute of metallization that has been observed to cause electrical degradation - increased contact resistance due to Schottky barrier formation. In this example basic semiconductor theory was able to provide an understanding of the electrical effects observed during accelerated stress testing.

Lathrop, J. W.↗

Alternative Test Methods for Electronic Parts

It is common practice within NASA to test electronic parts at the manufacturing lot level to demonstrate, statistically, that parts from the lot tested will not fail in service using generic application conditions. The test methods and the generic application conditions used have been developed over the years through cooperation between NASA, DoD, and industry in order to establish a common set of standard practices. These common practices, found in MIL-STD-883, MIL-STD-750, military part specifications, EEE-INST-002, and other guidelines are preferred because they are considered to be effective and repeatable and their results are usually straightforward to interpret. These practices can sometimes be unavailable to some NASA projects due to special application conditions that must be addressed, such as schedule constraints, cost constraints, logistical constraints, or advances in the technology that make the historical standards an inappropriate choice for establishing part performance and reliability. Alternate methods have begun to emerge and to be used by NASA programs to test parts individually or as part of a system, especially when standard lot tests cannot be applied. Four alternate screening methods will be discussed in this paper: Highly accelerated life test (HALT), forward voltage drop tests for evaluating wire-bond integrity, burn-in options during or after highly accelerated stress test (HAST), and board-level qualification.

Plante, Jeannette↗

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗

Different Approaches for Ensuring Performance/Reliability of Plastic Encapsulated Microcircuits (PEMs) in Space Applications

Engineers within the commercial and aerospace industries are using trade-off and risk analysis to aid in reducing spacecraft system cost while increasing performance and maintaining high reliability. In many cases, Commercial Off-The-Shelf (COTS) components, which include Plastic Encapsulated Microcircuits (PEMs), are candidate packaging technologies for spacecrafts due to their lower cost, lower weight and enhanced functionality. Establishing and implementing a parts program that effectively and reliably makes use of these potentially less reliable, but state-of-the-art devices, has become a significant portion of the job for the parts engineer. Assembling a reliable high performance electronic system, which includes COTS components, requires that the end user assume a risk. To minimize the risk involved, companies have developed methodologies by which they use accelerated stress testing to assess the product and reduce the risk involved to the total system. Currently, there are no industry standard procedures for accomplishing this risk mitigation. This paper will present the approaches for reducing the risk of using PEMs devices in space flight systems as developed by two independent Laboratories. The JPL procedure involves primarily a tailored screening with accelerated stress philosophy while the APL procedure is primarily, a lot qualification procedure. Both Laboratories successfully have reduced the risk of using the particular devices for their respective systems and mission requirements.

Gerke, R. David↗

Reliability and engineering sciences area. Materials research: Single junction thin film

A test bench was designed and fabricated for the purpose of improving control of hot-spot test accuracy. Electrochemical corrosion research focused on corrosion mechanisms to which both crystalline and a-Si modules may be subjected in central station applications. A variety of cells and several designs were subjected to accelerated stress tests. Humiditiy degradation rates were determined and key electrochemical failure mechanisms were identified. Software was developed for the prediction of power loss resulting from open circuits in an array field of a-Si modules. Failure analysis was continued on the four ARCO Solar Genesis modules. The interactions of water on the silicon module was examined. An autocatalytic photooxidation model was proposed. The reliability and durability of bonding materials and electrical insulation were also studied.

Source record↗

Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications

A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.

Sharma, Asbok K.↗