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NASA NTRS2001

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Powell, J. Anthony↗

NASA NTRS2010

Slopes To Prevent Trapping of Bubbles in Microfluidic Channels

The idea of designing a microfluidic channel to slope upward along the direction of flow of the liquid in the channel has been conceived to help prevent trapping of gas bubbles in the channel. In the original application that gave rise to this idea, the microfluidic channels are parts of micro-capillary electrophoresis (microCE) devices undergoing development for use on Mars in detecting compounds indicative of life. It is necessary to prevent trapping of gas bubbles in these devices because uninterrupted liquid pathways are essential for sustaining the electrical conduction and flows that are essential for CE. The idea is also applicable to microfluidic devices that may be developed for similar terrestrial microCE biotechnological applications or other terrestrial applications in which trapping of bubbles in microfluidic channels cannot be tolerated. A typical microCE device in the original application includes, among other things, multiple layers of borosilicate float glass wafers. Microfluidic channels are formed in the wafers, typically by use of wet chemical etching. The figure presents a simplified cross section of part of such a device in which the CE channel is formed in the lowermost wafer (denoted the channel wafer) and, according to the present innovation, slopes upward into a via hole in another wafer (denoted the manifold wafer) lying immediately above the channel wafer. Another feature of the present innovation is that the via hole in the manifold wafer is made to taper to a wider opening at the top to further reduce the tendency to trap bubbles. At the time of reporting the information for this article, an effort to identify an optimum technique for forming the slope and the taper was in progress. Of the techniques considered thus far, the one considered to be most promising is precision milling by use of femtosecond laser pulses. Other similar techniques that may work equally well are precision milling using a focused ion beam, or a small diamond-tipped drill bit.

Greer, Harold E.↗

NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A. D↗

NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan d, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 µ m thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan d with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan d ~ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan d in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· d = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· d = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A D↗

DOE OSTI2021

Method of fabricating photosensitive devices with reduced process-temperature budget

A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.

Kay, Randolph R.↗

DOE OSTI2020

Impact of undoped substrates on high performance silicon solar cells

Today's highest-efficiency silicon solar cells typically operate near the threshold between low-level and high-level injection. It is not well understood if pushing further into a regime in which the cell operating point is solidly in high-level injection at all times of the day has further benefits for the solar cell performance. From a reliability perspective, cells fabricated on lower doped silicon have a larger breakdown voltage. This advantage can affect the design of modules allowing higher voltages and a relaxation of the number of bypass diodes needed. In this project, we present a comprehensive assessment, both experimental and using simulation, of how bulk resistivity, light intensity, and operation temperature impact the performance of the silicon solar cell. This work incorporates a comprehensive device physics analysis assisted by numerical simulation. The source code is now available under General Public License (GPL3), and to further leverage the findings of this project and outreach people outside of the scientific community, we are working with www.pveducation.org (which receives >1 million visitors a year) to create interactive content using our simulation results. The simulation results indicate that high bulk resistivity wafers (>>10 Ωcm) require bulk Shockley-Read-Hall (SRH) lifetimes in the millisecond range to outperform wafers with standard bulk resistivities (<10 Ωcm). Additionally, above bulk resistivities of 10 Ωcm (the exact value depends on the bulk characteristics of the wafer), the cell efficiency is weakly dependent on the bulk resistivity. As a result, ingot manufactures may have an opportunity to further reduce wafer cost by growing higher resistivity ingots that are more tolerant to resistivity variations. This project is particularly relevant today, as solar cell architectures with improved surface passivation and milliseconds lifetimes wafers are commercially available, leveraging potential benefits of using higher bulk resistivities. Outside of interdigitated back contact (IBC) cell, reported studies on high resistivity silicon (>100 Ωcm) are very limited. To the best of our knowledge, this project provides for the first-time experimental insight on solar cells fabricated on wafers with bulk resistivities up to several thousand Ωcm, delivering a comprehensive vision of their performance under real-world temperature and light intensity operation conditions. We manufactured and characterized solar cells with bulk resistivities in the range of 1 Ωcm to >15k Ωcm. Under standard testing conditions (STC), we measured solar cells efficiencies over 20% over the entire range of bulk resistivities, using our baseline cell processing. To evaluate the cell performance in real-world operation conditions, the solar cells were measured at different temperatures (25-80°C) and at different light intensities (0.1-1 suns). The measurements show that the bulk resistivity does not impact the solar cell response to temperature and light intensity. Similar thermal coefficients (TC) were measured for standard and high bulk resistivities, and they are comparable with the TC values reported in the literature for standard bulk resistivities <10 Ωcm. After light soaking, the solar cell didn’t show signs of light-induced degradation (LID). This result was expected since n-type float zone (FZ) wafers were used in this work, i.e. low traces of boron and low concentration of oxygen (oxygen is typically found in the seed end of Czochralski (CZ) ingots). We measured for high bulk resistivities (>10 Ωcm) extremely high breakdown voltages (>1000V). In conclusion, the insight provided by this project can positively impact the levelized cost of energy (LCOE) of the photovoltaic systems through its effect on cell and ingot manufacturing yield, silicon cell power output, and module reliability.

14 SOLAR ENERGY↗

DOE OSTI2022

Fine Pitch Bonding for High Density Interconnects

CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Low-cost, high-efficiency III-V photovoltaics enabled by remote epitaxy through graphene (Final Technical Report)

One of the most important outcomes of this project was that the team developed a method to directly grow graphene layer in wafer-scale on III-V substrates. Conventionally, graphene had to be transferred for remote epitaxy, which has imposed significant challenges in scalability, film quality, and substrate recycling, due to the transfer-related issues. The newly developed method of directly forming 2D layers by Metal-Organic Chemical Vapor Deposition (MOCVD) has realized wafer-scale, defect-free graphene formation for remote epitaxy, which has huge implications not only for solar cells but also in expanding the scalability and the possibility for heterointegration with dissimilar material platforms. Another important outcome was on better understanding of remote epitaxy mechanism. The growth of III-V on graphene is vastly different from directly growing films on III-V substrates, because the surface energy of graphene is very small, meaning that the nucleation density on graphene will be much lower than exposed III-V surfaces. Also, the graphene and the interface properties critically affect remote interaction through graphene. With this obtained knowledge regarding III-V remote epitaxy, we were able to achieve wafer-scale single-crystalline remote epitaxy, 100% exfoliation of the remote epitaxial films, as well as multiple times of GaAs wafer reusability demonstration. The general rule of thumbs found during this project will be a stepping stone for the growth and fabrication of various high-performance devices by remote epitaxy. Lastly, because remote epitaxy and 2DLT offer a pathway to isolate single-crystal membranes from the host wafers, the wafer-scale remote epitaxy processes developed in this project could open up pathways for new functionality and multi-functionality by heterointegration of remote epitaxially formed membranes.

14 SOLAR ENERGY↗

DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗

NASA NTRS1980

The reverse laser drilling of transparent materials

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

Anthony, T. R.↗

NASA NTRS1994

Development of microchannel plate x-ray optics

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

Kaaret, Philip↗

NASA NTRS2006

An Update on Structural Seal Development at NASA GRC

A viewgraph presentation describing advanced structural seal development for NASA exploration is shown. The topics include: 1) GRC Structural Seals Team Research Areas; 2) Research Areas & Objective; 3) Wafer Seal Geometry/Flow Investigations; 4) Wafer Seal Installation DOE Study; 5) Results of Wafer Seal Installation DOE Study; 6) Wafer Geometry Study: Thickness Variations; 7) Wafer Geometry Study: Full-Size vs. Half-Size Wafers; 8) Spring Tube Seal Development; 9) Resiliency Improvement for Rene 41 Spring Tube; 10) Spring Tube Seals: Go-Forward Plan; 11) High Temperature Seal Preloader Development: TZM Canted Coil Spring; 12) TZM Canted Coil Spring Development; 13) Arc Jet Test Rig Development; and 14) Arc Jet Test Rig Status.

Dunlap, Pat↗

NASA NTRS2010

Fabrication and Modification of Nanoporous Silicon Particles

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion etching (RIE), may be applied to make the surface rough. This helps remove the nucleation layer. A protective layer is then deposited on the wafer. The protective layer, such as silicon nitride film or photoresist film, protects the wafer from electrochemical etching in an HF-based solution. A lithography technique is applied to pattern the particles onto the protective film. The undesired area of the protective film is removed, and the protective film on the back side of the wafer is also removed. Then the pattern is exposed to HF/surfactant solution, and a larger DC electrical current is applied to the wafers for a selected time. This step removes the nucleation layer. Then a DC current is applied to generate the nanopores. Next, a large electrical current is applied to generate a release layer. The particles are mechanically suspended in the solvent and collected by filtration or centrifuge.

Ferrari, Mauro↗

NASA NTRS2005

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Kaul, Anupama↗

NASA NTRS2005

Modifications of Fabrication of Vibratory Microgyroscopes

A micromachining process for the fabrication of vibratory microgyroscopes from silicon wafers, and aspects of the microgyroscope design that are inextricably linked with the fabrication process, have been modified in an effort to increase production yields from perspectives of both quantity and quality. Prior to the modifications, the effective production yield of working microgyroscopes was limited to one or less per wafer. The modifications are part of a continuing effort to improve the design and increase production yields to more than 30 working microgyroscopes per wafer. A discussion of pertinent aspects of the unmodified design and the unmodified fabrication process is prerequisite to a meaningful description of the modifications. The design of the microgyroscope package was not conducive to high yield and rapid testing of many microgyroscopes. One of the major impediments to high yield and testing was found to lie in vibration- isolation beams around the four edges of each microgyroscope, which beams were found to be unnecessary for achieving high resonance quality factors (Q values) characterizing the vibrations of petallike cantilevers. The fabrication process included an 8- m-deep plasma etch. The purpose of the etch was to create 8- m vertical gaps, below which were to be placed large gold evaporated electrodes and sensing pads to drive and sense resonant vibrations of the "petals." The process also included a step in which bridges between dies were cut to separate the dies. The etched areas must be kept clean and smooth (free of debris and spikes), because any object close to 8 m high in those areas would stop the vibrations. However, it was found that after the etch, there remained some spikes with heights that were, variously, almost as high or as high as the etch depth. It also was found that the cutting of bridges created silicon debris, some of which lodged in the 8- m gaps and some of which landed on top of the petals. The masses added to the petals by the debris altered resonance frequencies and/or Q values to unacceptable degrees. Hence, the spikes and the debris have been conjectured to cause most of the observed malfunctions of newly fabricated microgyroscopes. Another pertinent aspect of the unmodified design and process was the fabrication of electrodes and the 8- m capacitance gap on a 500- m-thick wafer, and the fabrication of a 3-mm-thick baseplate from another wafer. It was necessary to bond these wafers to each other in an assembly step that was later found to be superfluous in that it could be eliminated by a suitable modification of the design.

Bae, Sam Y.↗

NASA NTRS2012

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

The Cosmology Large Angular Scale Surveyor (CLASS) is a ground-based instrument that will measure the polarization of the cosmic microwave background to search for evidence for gravitational waves from a posited epoch of inflation early in the Universe s history. This measurement will require integration of superconducting transition-edge sensors with microwave waveguide inputs with excellent control of systematic errors, such as unwanted coupling to stray signals at frequencies outside of a precisely defined microwave band. To address these needs we present work on the fabrication of micromachined silicon, producing conductive quarter-wave backshort assemblies for the CLASS 40 GHz focal plane. Each 40 GHz backshort assembly consists of three degeneratively doped silicon wafers. Two spacer wafers are micromachined with through-wafer vias to provide a 2.04 mm long square waveguide delay section. The third wafer terminates the waveguide delay in a short. The three wafers are bonded at the wafer level by Au-Au thermal compression bonding then aligned and flip chip bonded to the CLASS detector at the chip level. The micromachining techniques used have been optimized to create high aspect ratio waveguides, silicon pillars, and relief trenches with the goal of providing improved out of band signal rejection. We will discuss the fabrication of integrated CLASS superconducting detector chips with the quarter-wave backshort assemblies.

Crowe, Erik J.↗

NASA NTRS2012

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

The Cosmology Large Angular Scale Surveyor (CLASS) is a ground-based instrument that will measure the polarization of the cosmic microqave background to search for gravitational waves form a posited epoch of inflation early in the universe's history. This measurement will require integration of superconducting transition-edge sensors with microwave waveguide inputs with good conrol of systematic errors, such as unwanted coupling to stray signals at frequencies outside of a precisely defined microwave band. To address these needs we will present work on the fabrication of silicon quarter-wave backshorts for the CLASS 40GHz focal plane. The 40GHz backshort consists of three degeneratively doped silicon wafers. Two spacer wafers are micromachined with through wafer vins to provide a 2.0mm long square waveguide. The third wafer acts as the backshort cap. The three wafers are bonded at the wafer level by Au-Au thermal compression bonding then aligned and flip chip bonded to the CLASS detector at the chip level. The micromachining techniques used have been optimized to create high aspect ratio waveguides, silicon pillars, and relief trenches with the goal of providing improved out of band signal rejection. We will discuss the fabrication of integrated CLASS superconducting detectors with silicon quarter wave backshorts and present current measurement results.

Crowe, Erik J.↗

NASA NTRS2014

Determining the Source of Water Vapor in a Cerium Oxide Electrochemical Oxygen Separator to Achieve Aviator Grade Oxygen

More than a metric ton of water is transported to the International Space Station (ISS) each year to provide breathing oxygen for the astronauts. Water is a safe and compact form of stored oxygen. The water is electrolyzed on ISS and ambient pressure oxygen is delivered to the cabin. A much smaller amount of oxygen is used each year in spacesuits to conduct Extra Vehicular Activities (EVAs). Space suits need high pressure (>1000 psia) high purity oxygen (must meet Aviator Breathing Oxygen "ABO" specifications, >99.5% O2). The water / water electrolysis system cannot directly provide high pressure, high purity oxygen, so oxygen for EVAs is transported to ISS in high pressure gas tanks. The tanks are relatively large and heavy, and the majority of the system launch weight is for the tanks and not the oxygen. Extracting high purity oxygen from cabin air and mechanically compressing the oxygen might enable on-board production of EVA grade oxygen using the existing water / water electrolysis system. This capability might also benefit human spaceflight missions, where oxygen for EVAs could be stored in the form of water, and converted into high pressure oxygen on-demand. Cerium oxide solid electrolyte-based ion transport membranes have been shown to separate oxygen from air, and a supported monolithic wafer form of the CeO2 electrolyte membrane has been shown to deliver oxygen at pressures greater than 300 psia. These supported monolithic wafers can withstand high pressure differentials even though the membrane is very thin, because the ion transport membrane is supported on both sides (Fig 1). The monolithic supported wafers have six distinct layers, each with matched coefficients of thermal expansion. The wafers are assembled into a cell stack which allows easy air flow across the wafers, uniform current distribution, and uniform current density (Fig 2). The oxygen separation is reported to be "infinitely selective" to oxygen [1] with reported purity of 99.99% [2]. Combined with a mechanical compressor, a Solid Electrolyte Oxygen Separator (SEOS) should be capable of producing ABO grade oxygen at pressures >2400 psia, on the space station. Feasibility tests using a SEOS integrated with a mechanical compressor identified an unexpected contaminant in the oxygen: water vapour was found in the oxygen product, sometimes at concentrations higher than 40 ppm (the ABO limit for water vapour is 7 ppm). If solid electrolyte membranes are really "infinitely selective" to oxygen as they are reported to be, where did the water come from? If water is getting into the oxygen, what other contaminants might get into the oxygen? Microscopic analyses of wafers, welds, and oxygen delivery tubes were performed in an attempt to find the source of the water vapour contamination. Hot and cold pressure decay tests were performed. Measurements of water vapour as a function of O2 delivery rate, O2 delivery pressure, and process air humidity levels were the most instructive in finding the source of water contamination (Fig 3). Water contamination was directly affected by oxygen delivery rate (doubling the oxygen production rate cut the water level in half). Water was affected by process air humidity levels and delivery pressure in a way that indicates the water was diffusing into the oxygen delivery system.

Graf, John↗