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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

A synchronized computational architecture for generalized bilateral control of robot arms

This paper describes a computational architecture for an interconnected high speed distributed computing system for generalized bilateral control of robot arms. The key method of the architecture is the use of fully synchronized, interrupt driven software. Since an objective of the development is to utilize the processing resources efficiently, the synchronization is done in the hardware level to reduce system software overhead. The architecture also achieves a balaced load on the communication channel. The paper also describes some architectural relations to trading or sharing manual and automatic control.

Bejczy, Antal K.↗
NASA NTRS1989

Synchronous critical speed tracking in hydrostatic bearing supported rotors

Hydrostatic bearings used in advanced turbopump designs use the pumped propellant as the working fluid and supply the propellant to the bearing from pump discharge. The resulting rotordynamic coefficients are highly speed-dependent and in some instances can cause system natural frequencies to coincide with spin speed over a wide speed range. This paper discusses this 'synchronous tracking' phenomenon. The factors affecting it are defined, and specific examples are presented. Methods which identify synchronous tracking issues early in the design process are reported, and techniques for eliminating this undesirable characteristic are addressed.

Henderson, Thomas W.↗
NASA NTRS1990

Carrying Synchronous Voice Data On Asynchronous Networks

Buffers restore synchronism for internal use and permit asynchronism in external transmission. Proposed asynchronous local-area digital communication network (LAN) carries synchronous voice, data, or video signals, or non-real-time asynchronous data signals. Network uses double buffering scheme that reestablishes phase and frequency references at each node in network. Concept demonstrated in token-ring network operating at 80 Mb/s, pending development of equipment operating at planned data rate of 200 Mb/s. Technique generic and used with any LAN as long as protocol offers deterministic (or bonded) access delays and sufficient capacity.

Bergman, Larry A.↗
NASA NTRS1989

Frame synchronization methods based on channel symbol measurements

The current DSN frame synchronization procedure is based on monitoring the decoded bit stream for the appearance of a sync marker sequence that is transmitted once every data frame. The possibility of obtaining frame synchronization by processing the raw received channel symbols rather than the decoded bits is explored. Performance results are derived for three channel symbol sync methods, and these are compared with results for decoded bit sync methods reported elsewhere. It is shown that each class of methods has advantages or disadvantages under different assumptions on the frame length, the global acquisition strategy, and the desired measure of acquisition timeliness. It is shown that the sync statistics based on decoded bits are superior to the statistics based on channel symbols, if the desired operating region utilizes a probability of miss many orders of magnitude higher than the probability of false alarm. This operating point is applicable for very large frame lengths and minimal frame-to-frame verification strategy. On the other hand, the statistics based on channel symbols are superior if the desired operating point has a miss probability only a few orders of magnitude greater than the false alarm probability. This happens for small frames or when frame-to-frame verifications are required.

Dolinar, S.↗
NASA NTRS1990

The cost of conservative synchronization in parallel discrete event simulations

The performance of a synchronous conservative parallel discrete-event simulation protocol is analyzed. The class of simulation models considered is oriented around a physical domain and possesses a limited ability to predict future behavior. A stochastic model is used to show that as the volume of simulation activity in the model increases relative to a fixed architecture, the complexity of the average per-event overhead due to synchronization, event list manipulation, lookahead calculations, and processor idle time approach the complexity of the average per-event overhead of a serial simulation. The method is therefore within a constant factor of optimal. The analysis demonstrates that on large problems--those for which parallel processing is ideally suited--there is often enough parallel workload so that processors are not usually idle. The viability of the method is also demonstrated empirically, showing how good performance is achieved on large problems using a thirty-two node Intel iPSC/2 distributed memory multiprocessor.

Nicol, David M.↗
NASA NTRS1990

Hardware-assisted software clock synchronization for homogeneous distributed systems

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Ramanathan, P.↗
NASA NTRS1991

Improved Notch Filter For Synchronous-Response Control

Tracking differential-notch filter (TDNF) developed to retain good synchronous-response performance of notch filter, but with vastly improved stability properties. Measurement error perfectly filtered from feedback signal used to drive compensator. Provides good stability of simple lead/lag compensator combined with good synchronous-response performance gained by addition of notch filter.

Johnson, Bruce G.↗
NASA NTRS1990

Digitized synchronous demodulator

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.

Woodhouse, Christopher E.↗
NASA NTRS1991

Synchronously deployable double fold beam and planar truss structure

A deployable structure that synchronously deploys in both length and width is disclosed which is suitable for use as a structural component for orbiting space stations or large satellites. The structure is designed with maximum packing efficiency so that large structures may be collapsed and transported in the cargo bay of the Space Shuttle. The synchronous deployment feature allows the structure to be easily deployed in space by two astronauts, without a complex deployment mechanism. The structure is made up of interconnected structural units, each generally in the shape of a parallelepiped. The structural units are constructed of structural members connected with hinged and fixed connections at connection nodes in each corner of the parallelepiped. Diagonal members along each face of the parallelepiped provide structural rigidity and are equipped with mid-length, self-locking hinges to allow the structure to collapse. The structure is designed so that all hinged connections may be made with simple clevis-type hinges requiring only a single degree of freedom, and each hinge pin is located along the centerline of its structural member for increased strength and stiffness.

Rhodes, Marvin D.↗
NASA NTRS1992

Improved Analog Synchronous Demodulator

Improved analog synchronous demodulator uses input filtering, differential amplification, and synchronized switching in such way output ripple suppressed without need for output filter, and output responds rapidly (within clock cycle) to change in level of demodulated signal.

Sutton, John F.↗
NASA NTRS1990

An application for multi-person task synchronization

Computer applications are studied that will enable a group of people to synchronize their actions when following a predefined task sequence. It is assumed that the people involved only have computer workstations available to them for communication. Hence, the approach is to study how the computer can be used to help a group remain synchronized. A series of applications were designed and developed that can be used as vehicles for experimentation. An example of how this technique can be used for a remote coaching capability is explained in a report describing an experiment that simulated a Life Sciences experiment on-board Space Station Freedom, with a ground based principal investigator providing the expertise by coaching the on-orbit mission specialist.

Brown, Robert L.↗
NASA NTRS1990

Synchronization of autonomous objects in discrete event simulation

Autonomous objects in event-driven discrete event simulation offer the potential to combine the freedom of unrestricted movement and positional accuracy through Euclidean space of time-driven models with the computational efficiency of event-driven simulation. The principal challenge to autonomous object implementation is object synchronization. The concept of a spatial blackboard is offered as a potential methodology for synchronization. The issues facing implementation of a spatial blackboard are outlined and discussed.

Rogers, Ralph V.↗
NASA NTRS1992

Digital synchronization and communication techniques

Information on digital synchronization and communication techniques is given in viewgraph form. Topics covered include phase shift keying, modems, characteristics of open loop digital synchronizers, an open loop phase and frequency estimator, and a digital receiver structure using an open loop estimator in a decision directed architecture.

Lindsey, William C.↗
NASA NTRS1992

Experimental validation of clock synchronization algorithms

The objective of this work is to validate mathematically derived clock synchronization theories and their associated algorithms through experiment. Two theories are considered, the Interactive Convergence Clock Synchronization Algorithm and the Midpoint Algorithm. Special clock circuitry was designed and built so that several operating conditions and failure modes (including malicious failures) could be tested. Both theories are shown to predict conservative upper bounds (i.e., measured values of clock skew were always less than the theory prediction). Insight gained during experimentation led to alternative derivations of the theories. These new theories accurately predict the behavior of the clock system. It is found that a 100 percent penalty is paid to tolerate worst-case failures. It is also shown that under optimal conditions (with minimum error and no failures) the clock skew can be as much as three clock ticks. Clock skew grows to six clock ticks when failures are present. Finally, it is concluded that one cannot rely solely on test procedures or theoretical analysis to predict worst-case conditions.

Palumbo, Daniel L.↗
NASA NTRS1992

An extension to Schneider's general paradigm for fault-tolerant clock synchronization

In 1987, Schneider presented a general paradigm that provides a single proof of a number of fault tolerant clock synchronization algorithms. His proof was subsequently subjected to the rigor of mechanical verification by Shankar. However, both Schneider and Shankar assumed a condition Shankar refers to as a bounded delay. This condition states that the elapsed time between synchronization events (i.e., the time that the local process applies an adjustment to its logical clock) is bounded. This property is really a result of the algorithm and should not be assumed in a proof of correctness. This paper remedies this by providing a proof of this property in the context of the general paradigm proposed by Schneider. The argument given is a generalization of Welch and Lynch's proof of a related property for their algorithm.

Miner, Paul S.↗
NASA NTRS1973

Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

Source record↗
NASA NTRS1993

Synchronizing A Stroboscope With A Video Camera

Circuit synchronizes flash of light from stroboscope with frame and field periods of video camera. Sync stripper sends vertical-synchronization signal to delay generator, which generates trigger signal. Flashlamp power supply accepts delayed trigger signal and sends pulse of power to flash lamp. Designed for use in making short-exposure images that "freeze" flow in wind tunnel. Also used for making longer-exposure images obtained by use of continuous intense illumination.

Rhodes, David B.↗
NASA NTRS1993

Virtually-synchronous communication based on a weak failure suspector

Failure detectors (or, more accurately Failure Suspectors (FS)) appear to be a fundamental service upon which to build fault-tolerant, distributed applications. This paper shows that a FS with very weak semantics (i.e., that delivers failure and recovery information in no specific order) suffices to implement virtually-synchronous communication (VSC) in an asynchronous system subject to process crash failures and network partitions. The VSC paradigm is particularly useful in asynchronous systems and greatly simplifies building fault-tolerant applications that mask failures by replicating processes. We suggest a three-component architecture to implement virtually-synchronous communication: (1) at the lowest level, the FS component; (2) on top of it, a component (2a) that defines new views; and (3) a component (2b) that reliably multicasts messages within a view. The issues covered in this paper also lead to a better understanding of the various membership service semantics proposed in recent literature.

Schiper, Andre↗