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At least 343 records · Page 19

Electronegative metal dopants improve switching variability in Al 2 ⁢O 3 resistive switching devices

Resistive random-access memories are promising for nonvolatile memory and brain-inspired computing applications. High variability and low yield of these devices are key drawbacks hindering reliable training of physical neural networks. In this paper, we show that doping an oxide electrolyte, Al 2 ⁢O 3 , with electronegative metals makes resistive switching significantly more reproducible, surpassing the reproducibility requirements for obtaining reliable hardware neuromorphic circuits. Based on density functional theory calculations, the underlying mechanism is hypothesized to be the ease of creating oxygen vacancies in the vicinity of electronegative dopants due to the capture of the associated electrons by dopant midgap states and the weakening of Al-O bonds. These oxygen vacancies and vacancy clusters also bind significantly to the dopant, thereby serving as preferential sites and building blocks in the formation of conducting paths. Throughout this work, we validate this theory experimentally by implanting different dopants over a range of electronegativities in devices made of multiple alternating layers of Al 2 ⁢O 3 and WN and find superior repeatability and yield with highly electronegative metals, Au, Pt, and Pd. These devices also exhibit a gradual SET transition, enabling multibit switching that is desirable for analog computing.

36 MATERIALS SCIENCE↗

Interfacial magnetic characteristics of nearly compensated gadolinium iron garnet

Reports on spin Hall magnetoresistance, magnonic spin currents from thermal gradients, and spin transfertorque magnetic random-access memory using compensated ferrimagnets largely discuss bulk magnetization but lack consideration of depth profiles or interfacial characteristics. Here, magnetic and structural characterization of profiles and interfaces was performed for nearly compensated gadolinium iron garnet (GdIG) thin films. X-ray diffraction and reciprocal space maps show that sputter deposited GdIG on Si is polycrystalline with the desired cubic garnet phase, and GdIG on gadolinium gallium garnet (GGG) is epitaxial with <0.06% compressive strain. Temperature-dependent magnetometry confirms the compensation temperatures of GGG/GdIG and Si/GdIG to be 285 and 260 K, respectively, both near room temperature. Interestingly, these measurements suggest the presence of unsaturated rare-earth moments, which result in a characteristic hysteresis between heating and cooling sequences in the magnetization-temperature curves at zero field. Depth-profile measurements from polarized neutron reflectometry (PNR) indicate up to 91% volume fraction in GdIG on Si. At the interface, PNR reveals a region containing magnetized Fe-doped GGG, a low-density GdIG at the GGG/GdIG interface, and a thin magnetically dead layer at the Si/GdIG interface. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy confirm the assessment of PNR. In conclusion, the magnetic characteristics of interfacial regions are attributed to intermixing of Fe-Ga at the GGG/GdIG interface and the presence of amorphous Fe-Si at the Si/GdIG interface.

36 MATERIALS SCIENCE↗

Electrical control of magnetism by electric field and current-induced torques

The remanent magnetization of ferromagnets has long been studied and used to store binary information. While early magnetic memory designs relied on magnetization switching by locally generated magnetic fields, key insights in condensed matter physics later suggested the possibility of doing it by electrical means instead. In the 1990s, Slonczewski and Berger formulated the concept of current-induced spin torques in magnetic multilayers through which a spin-polarized current generated by a first ferromagnet may be used to switch the magnetization of a second one. This discovery drove the development of spin-transfer-torque magnetic random-access memories (MRAMs). More recent fundamental research revealed other types of current-induced torques named spin-orbit torques (SOTs) and will lead to a new generation of devices including SOT MRAMs and skyrmion-based devices. Parallel to these advances, multiferroics and their magnetoelectric coupling, first investigated experimentally in the 1960s, experienced a renaissance. Dozens of multiferroic compounds with new magnetoelectric coupling mechanisms were discovered and high-quality multiferroic films were synthesized (notably of BiFeO 3 ), also leading to novel device concepts for information and communication technology such as the magnetoelectric spin-orbit (MESO) transistor. The story of the electrical switching of magnetization, which is discussed in this review, is that of a dance between fundamental research (in spintronics, condensed matter physics, and materials science) and technology (MRAMs, MESO transistors, microwave emitters, spin diodes, skyrmion-based devices, components for neuromorphics, etc.). This pas de deux has led to major scientific and technological breakthroughs in recent decades (such as the conceptualization of pure spin currents, the observation of magnetic skyrmions, and the discovery of spin-charge interconversion effects). As a result, this field has not only propelled MRAMs into consumer electronics products but also fueled discoveries in adjacent research areas such as ferroelectrics or magnonics. Here, in this review, recent advances in the control of magnetism by electric fields and by current-induced torques are covered. Fundamental concepts in these two directions are reviewed first, their combination is then discussed, and finally current various families of devices harnessing the electrical control of magnetic properties for various application fields are addressed. The review concludes by giving perspectives in terms of both emerging fundamental physics concepts and new directions in materials science.

36 MATERIALS SCIENCE↗

Exploring Memory Hierarchy to Improve Scientific Data Read Performance, In: 2015 IEEE International Conference on Cluster Computing

Improving read performance is one of the major challenges with speeding up scientific data analytic applications. Utilizing the memory hierarchy is one major line of researches to address the read performance bottleneck. Related methods usually combine solide-state-drives(SSDs) with dynamic random-access memory(DRAM) and/or parallel file system(PFS) to mitigate the speed and space gap between DRAM and PFS. However, these methods are unable to handle key performance issues plaguing SSDs, namely read contention that may cause up to 50% performance reduction. In this paper, we propose a framework that exploits the memory hierarchy resource to address the read contention issues involved with SSDs. The framework employs a general purpose online read algorithm that able to detect and utilize memory hierarchy resource to relieve the problem. To maintain a near optimal operating environment for SSDs, the framework is able to orchastrate data chunks across different memory layers to facilitate the read algorithm. Compared to existing tools, our framework achieves up to 50% read performance improvement when tested on datasets from real-world scientific simulations.

Computer Science↗

Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

In this paper, we present a scalable digital hardware accelerator based on non-volatile memory arrays capable of realizing deep convolutional spiking neural networks (SNNs). Our design studies are conducted using a compact model for spin-transfer torque random access memory (STT-RAM) devices. Large networks are realized by tiling multiple cores which communicate by transmitting spike packets via an on-chip routing network. Compared to an equivalent SRAM based core design, we show that the STT-RAM based design achieves nearly 15X higher GSOPS (Synaptic Operations per Second) per Watt per mm 2 making it a promising platform for realizing systems with significant area and power limitations.

Kulkarni, Shruti↗

SharP: Towards Programming Extreme-Scale Systems with Hierarchical Heterogeneous Memory

The pre-exascale systems are expected to have a significant amount of hierarchical and heterogeneous on-node memory, and this trend of system architecture in extreme-scale systems is expected to continue into the exascale era. Along with hierarchical-heterogeneous memory, the system typically has a high-performing network and a compute accelerator. This system architecture is not only effective for running traditional High Performance Computing (HPC) applications (Big-Compute), but also running data-intensive HPC applications and Big-Data applications. As a consequence, there is a growing desire to have a single system serve the needs of both Big-Compute and Big-Data applications. Though the system architecture supports the convergence of the Big-Compute and Big-Data, the programming models have yet to evolve to support either hierarchical-heterogeneous memory systems or the convergence. In this work, we propose and develop the programming abstraction called SHARed data-structure centric Programming abstraction (SharP) to address both of these goals, i.e., provide (1) a simple, usable, and portable abstraction for hierarchical-heterogeneous memory and (2) a unified programming abstraction for Big-Compute and Big-Data applications. To evaluate SharP, we implement a Stencil benchmark using SharP, port QMCPack, a petascale-capable application, and adapt Memcached ecosystem, a popular Big-Data framework, to use SharP, and quantify the performance and productivity advantages. Additionally, we demonstrate the simplicity of using SharP on different memories including DRAM, High-bandwidth Memory (HBM), and non-volatile random access memory (NVRAM).

97 MATHEMATICS AND COMPUTING↗

Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking

In this article, we study the limits of the number of capacitors and read history dependence in a 2T-nC ferroelectric random-access memory (FeRAM) cell, paving the way for its high-density integration toward hundreds of stacked layers. Through a comprehensive experimental and simulation study on the scaling behavior of the 2T-nC FeRAM architecture, we demonstrate: (i) successful fabrication of 2T-64C cells with robust memory operation and clearly distinguishable ‘0’ and ‘1’ states, even in 64- capacitor configurations; (ii) that the parasitic capacitance of the floating node originates predominantly from the linear component of the ferroelectric capacitor, and its impact on n-scaling—due to degraded sense margin—can be mitigated by floating unselected capacitors with enough TΩ isolation; (iii) that sharing write and read transistors among n capacitors introduces a read history dependence issue due to fluctuating floating node voltage (VFN); and (iv) that a proposed FN discharge scheme can effectively eliminate read-sequence dependence, at the cost of reduced read endurance.

36 MATERIALS SCIENCE↗

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗

First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and its Scalability for High-Density 3D Ferroelectric Capacitor Memory

In this article, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; V ) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for Vw/2 scheme and worsens the Vw/3 scheme as disturb increases to intolerable 2Vw/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (Cz).

42 ENGINEERING↗

UPC++: A PGAS extension for C++

Partitioned Global Address Space (PGAS) languages are convenient for expressing algorithms with large, random-access data, and they have proven to provide high performance and scalability through lightweight one-sided communication and locality control. While very convenient for moving data around the system, PGAS languages have taken different views on the model of computation, with the static Single Program Multiple Data (SPMD) model providing the best scalability. In this paper we present UPC++, a PGAS extension for C++ that has three main objectives: 1) to provide an object-oriented PGAS programming model in the context of the popular C++ language, 2) to add useful parallel programming idioms unavailable in UPC, such as asynchronous remote function invocation and multidimensional arrays, to support complex scientific applications, 3) to offer an easy on-ramp to PGAS programming through interoperability with other existing parallel programming systems (e.g., MPI, OpenMP, CUDA). We implement UPC++ with a 'compiler-free' approach using C++ templates and runtime libraries. We borrow heavily from previous PGAS languages and describe the design decisions that led to this particular set of language features, providing significantly more expressiveness than UPC with very similar performance characteristics. We evaluate the programmability and performance of UPC++ using five benchmarks on two representative supercomputers, demonstrating that UPC++ can deliver excellent performance at large scale up to 32K cores while offering PGAS productivity features to C++ applications.

Zheng, Y↗

A Hartree-Fock Application Using UPC++ and the New DArray Library

The Hartree-Fock (HF) method is the fundamental first step for incorporating quantum mechanics into many-electron simulations of atoms and molecules, and it is an important component of computational chemistry toolkits like NWChem. The GTFock code is an HF implementation that, while it does not have all the features in NWChem, represents crucial algorithmic advances that reduce communication and improve load balance by doing an up-front static partitioning of tasks, followed by work stealing whenever necessary. To enable innovations in algorithms and exploit next generation exascale systems, it is crucial to support quantum chemistry codes using expressive and convenient programming models and runtime systems that are also efficient and scalable. Here, this paper presents an HF implementation similar to GTFock using UPC++, a partitioned global address space model that includes flexible communication, asynchronous remote computation, and a powerful multidimensional array library. UPC++ offers runtime features that are useful for HF such as active messages, a rich calculus for array operations, hardware-supported fetch-and-add, and functions for ensuring asynchronous runtime progress. We present a new distributed array abstraction, DArray, that is convenient for the kinds of random-access array updates and linear algebra operations on block-distributed arrays with irregular data ownership. Finally, we analyze the performance of atomic fetch-and-add operations (relevant for load balancing) and runtime attentiveness, then compare various techniques and optimizations for each. Our optimized implementation of HF using UPC++ and the DArrays library shows up to 20% improvement over GTFock with Global Arrays at scales up to 24,000 cores.

97 MATHEMATICS AND COMPUTING↗

Atomically Thin CBRAM Enabled by 2-D Materials: Scaling Behaviors and Performance Limits

Reducing the energy and power dissipation of conductive bridge random access memory (CBRAM) cells is of critical importance for their applications in future Internet of Things (IoT) device and neuromorphic computing platforms. Atomically thin CBRAMs enabled by 2-D materials are studied theoretically by using 3-D kinetic Monte Carlo simulations together with experimental characterization. The results indicate the performance potential of attoJoule energy dissipation for intrinsic filament formation and a filament size of a single atomistic chain in such a CBRAM cell. The atomically thin CBRAM cells also show qualitatively different features from conventional CBRAM cells, including complete rupture of the filament in the reset stage and comparable forming and set voltages. The scaling and variability of the CBRAM cells down to sub-nanometer size of the switching layer as realized in the experiment are systematically studied, which indicates performance improvement and increased relative variability as the switching layer scales down. Finally, the results establish the ultimate limits of the size and energy scaling for CBRAM cells and illustrate the unique application of 2-D materials in ultralow power memory devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗

Validation techniques for fault emulation of SRAM-based FPGAs

A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA in a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this study we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.

98 NUCLEAR DISARMAMENT, SAFEGUARDS, AND PHYSICAL P↗

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibit a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Training a Neural Network on Analog TaO x ReRAM Devices Irradiated With Heavy Ions: Effects on Classification Accuracy Demonstrated With CrossSim

The image classification accuracy of a TaO x ReRAM-based neuromorphic computing accelerator is evaluated after intentionally inducing a displacement damage up to a fluence of 10 14 2.5-MeV Si ions/cm 2 on the analog devices that are used to store weights. Results are consistent with a radiation-induced oxygen vacancy production mechanism. When the device is in the high-resistance state during heavy ion radiation, the device resistance, linearity, and accuracy after training are only affected by high fluence levels. Here, the findings in this paper are in accordance with the results of previous studies on TaO x -based digital resistive random access memory. When the device is in the low-resistance state during irradiation, no resistance change was detected, but devices with a 4-kΩ inline resistor did show a reduction in accuracy after training at 10 14 2.5-MeV Si ions/cm 2 . This indicates that changes in resistance can only be somewhat correlated with changes to devices’ analog properties. This paper demonstrates that TaO x devices are radiation tolerant not only for high radiation environment digital memory applications but also when operated in an analog mode suitable for neuromorphic computation and training on new data sets.

42 ENGINEERING↗