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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1971

Architectural design and simulation of a virtual memory

Virtual memory is an imaginary main memory with a very large capacity which the programmer has at his disposal. It greatly contributes to the solution of the dynamic storage allocation problem. The architectural design of a virtual memory is presented which implements by hardware the idea of queuing and scheduling the page requests to a paging drum in such a way that the access of the paging drum is increased many times. With the design, an increase of up to 16 times in page transfer rate is achievable when the virtual memory is heavily loaded. This in turn makes feasible a great increase in the system throughput.

Kwok, G.↗
NASA NTRS1972

Optical read/write memory system components

The optical components of a breadboard holographic read/write memory system have been fabricated and the parameters specified of the major system components: (1) a laser system; (2) an x-y beam deflector; (3) a block data composer; (4) the read/write memory material; (5) an output detector array; and (6) the electronics to drive, synchronize, and control all system components. The objectives of the investigation were divided into three concurrent phases: (1) to supply and fabricate the major components according to the previously established specifications; (2) to prepare computer programs to simulate the entire holographic memory system so that a designer can balance the requirements on the various components; and (3) to conduct a development program to optimize the combined recording and reconstruction process of the high density holographic memory system.

Kozma, A.↗
NASA NTRS1973

Design, fabrication, testing and delivery of a feasibility model laminated ferrite memory

The effect of using multiword addressing with laminated ferrite arrays was made. Both a reduction in the number of components, and a reduction in power consumption was obtained for memory capacities between one million bits and one million words. An investigation into the effect of variations in the processing steps resulted in a number of process modifications that improved the quality of the arrays. A feasibility model laminated ferrite memory system was constructed by modifying a commercial plated wire memory system to operate with laminated ferrite arrays. To provide flexibility for the testing of the laminated ferrite memory, an exerciser has been constructed to automatically control the loading and recirculation of arbitrary size checkerboard patterns of one's and zero's and to display the patterns of stored information on a CRT screen.

Heckler, H. C.↗
NASA NTRS1974

A multiprocessor computer simulation model employing a feedback scheduler/allocator for memory space and bandwidth matching and TMR processing

A computer simulation model for a multiprocessor computer is developed that is useful for studying the problem of matching multiprocessor's memory space, memory bandwidth and numbers and speeds of processors with aggregate job set characteristics. The model assumes an input work load of a set of recurrent jobs. The model includes a feedback scheduler/allocator which attempts to improve system performance through higher memory bandwidth utilization by matching individual job requirements for space and bandwidth with space availability and estimates of bandwidth availability at the times of memory allocation. The simulation model includes provisions for specifying precedence relations among the jobs in a job set, and provisions for specifying precedence execution of TMR (Triple Modular Redundant and SIMPLEX (non redundant) jobs.

Bradley, D. B.↗
NASA NTRS1975

Short, unit-memory, Byte-oriented, binary convolutional codes having maximal free distance

It is shown that (n sub 0, k sub 0) convolutional codes with unit memory always achieve the largest free distance among all codes of the same rate k sub 0/n sub 0 and same number 2MK sub 0 of encoder states, where M is the encoder memory. A unit-memory code with maximal free distance is given at each place where this free distance exceeds that of the best code with k sub 0 and n sub 0 relatively prime, for all Mk sub 0 less than or equal to 6 and for R = 1/2, 1/3, 1/4, 2/3. It is shown that the unit-memory codes are byte-oriented in such a way as to be attractive for use in concatenated coding systems.

Lee, L. N.↗
NASA NTRS1975

Camera memory study for large space telescope

Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.

Hoffman, C. P.↗
NASA NTRS1975

The potential of multi-port optical memories in digital computing

A high-capacity memory with a relatively high data transfer rate and multi-port simultaneous access capability may serve as the basis for new computer architectures. The implementation of a multi-port optical memory is discussed. Several computer structures are presented that might profitably use such a memory. These structures include (1) a simultaneous record access system, (2) a simultaneously shared memory computer system, and (3) a parallel digital processing structure.

Alford, C. O.↗
NASA NTRS1976

RAPID: A random access picture digitizer, display, and memory system

RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

Yakimovsky, Y.↗
NASA NTRS1976

Test program for 4-K memory card, JOLT microprocessor

A memory test program is described for use with the JOLT microcomputer 4,096-word memory board used in development of an Omega navigation receiver. The program allows a quick test of the memory board by cycling the memory through all possible bit combinations in all words.

Lilley, R. W.↗
NASA NTRS1978

Strobe-margin test for plated memory systems

Technique measures performance of plated-wire memories. Strobe-margin test (SMT) utilizes worst-case testing and automatically gives exact strobe margin. Test is automatic; thus, memory system-level test is superior to tests at component level that use artificial test conditions. Test is significant tool in design and test of plated-wire memory systems. It can rapidly quantify memory-system margin on each production unit and impact of any design changes.

Anspach, T. E.↗
NASA NTRS1978

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Hayes, P. J.↗
NASA NTRS1978

The ILLIAC IV memory system: Current status and future possibilities

The future needs of researchers who will use the Illiac were examined and the requirements they will place on the memory system were evaluated. Various alternatives to replacing critical memory components were considered with regard to cost, risk, system impact, software requirements, and implementation schedules. The current system, its performance and status, and the limitations it places on possible enhancements are discussed as well as the planned enhancements to the Illiac processor. After a brief technology survey, different implementations are presented for each system memory component. Three different memory systems are proposed to meet the identified needs of the Illiac user community. These three alternatives differ considerably with respect to storage capacity and accessing capabilities, but they all offer significant improvements over the current system. The proposed systems and their relative merits are analyzed.

Stevenson, D. K.↗
NASA NTRS1980

Expanded interleaved solid-state memory for a wide bandwidth transient waveform recorder

An interleaved, solid state expanded memory for a 100 MHz bandwidth waveform recorder is described. The memory development resulted in a significant increase in the storage capacity of a commercially available recorder. The motivation for the memory expansion of the waveform recorder, which is used to support in-flight measurement of the electromagnetic characteristics of lightning discharges, was the need for a significantly longer data window than that provided by the commercially available unit. The expanded recorder provides a data window that is 128 times longer than the commercial unit, while maintaining the same time resolution, by increasing the storage capacity from 1024 to 131 072 data samples. The expanded unit operates at sample periods as small as 10 ns. Sampling once every 10 ns, the commercial unit records for about 10 microseconds before the memory is filled, whereas, the expanded unit records for about 1300 microseconds. A photo of the expanded waveform recorder is shown.

Thomas, R. M., Jr.↗
NASA NTRS1982

Optical Memory Stores 10 12sup. Bits

Optical Mass Memory has separate recorder (write) and reproducer (read) modules. Data are recorded on fiches and stored in a carrousel. Fische is retrieved from carrousel by transporter in under 10 seconds. Input to optical memory is standard TV camera. TV monitor at memory output displays stored video images when they are retrieved from fisches. Input to the optical memory can also be taken from pseudorandom sequence generator.

Source record↗
NASA NTRS1984

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗
NASA NTRS1983

Computer memory power control for the Galileo spacecraft

The developmental history, major design drives, and final topology of the computer memory power system on the Galileo spacecraft are described. A unique method of generating memory backup power directly from the fault current drawn during a spacecraft power overload or fault condition allows this system to provide continuous memory power. This concept provides a unique solution to the problem of volatile memory loss without the use of a battery of other large energy storage elements usually associated with uninterrupted power supply designs.

Detwiler, R. C.↗
NASA NTRS1986

Fast Initialization of Bubble-Memory Systems

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

Looney, K. T.↗
NASA NTRS1985

The number of stable points of an infinite-range spin glass memory

A rigorous asymptotic expression for the number of stable points of an infinite-range spin glass with independently identically distributed (i.i.d) zero-mean gaussian exchange interactions is discussed. The result also applies tot he number of stable points of a Hopfield Memory (a kind of associative memory) when the memory connections are i.i.d. zero-mean gaussians. The result is that the number of stable points is asymptotic to a constant slightly larger than 1 times 2 to a power slightly larger thann/4, where n is the number of spins in the glass, or the length of the n-tuples to be remembered by the memory. The answer is easily derived using simple asymptotic techniques from an exact expression for the probability that an arbitrary plus or minus 1 n-tuple of spins is a fixed point. This expression is obtained from the fact that any distribution of joint zero-mean gaussians of given covariances is specified solely by these covariances. This is a far shorter derivation of the result than those existing.

Posner, E. C.↗