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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Origin of “memory glass” effect in pressure-amorphized rare-earth molybdate single crystals

The memory glass effect (MGE) describes the ability of some materials to recover the initial structure and crystallographic orientation after pressure-induced amorphization (PIA). In spite of numerous studies the nature and underlying mechanisms of this phenomenon are still not clear. Here we report investigations of MGE in β′-Eu{sub 2}(MoO{sub 4}){sub 3} single crystal samples subjected to high pressure amorphization. Using the XRD and TEM techniques we carried out detailed analysis of the structural state of high pressure treated single crystal samples as well as structural transformations due to subsequent annealing at atmospheric pressure. The structure of the sample has been found to be complex, mainly amorphous, however, the amorphous medium contains evenly distributed nanosize inclusions of a paracrystalline phase. The inclusions are highly correlated in orientation and act as “memory units” in the MGE. - Graphical abstract: Schematic representation of pressure-induced amorphization and “memory glass” effect in rare-earth molybdate single crystals. The XRD and TEM measurements have revealed the presence of the residual identically oriented paracrystalline nanodomains in the pressure-amorphized state. These domains preserve the information about initial structure and orientation of the sample. They act as memory units and crystalline seeds during transformation of the amorphous phase back to the starting single crystalline one. - Highlights: • Pressure-amorphized Eu{sub 2}(MoO4){sub 3} single crystals were studied ex-situ by XRD and TEM. • Tiny residual crystalline inclusions were found in amorphous matrix of sample. • The inclusions keep in memory the parent crystal structure and orientation. • The inclusions account for “memory glass” effect in rare-earth molibdates.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2016

Multiple-stable anisotropic magnetoresistance memory in antiferromagnetic MnTe

Commercial magnetic memories rely on the bistability of ordered spins in ferromagnetic materials. Recently, experimental bistable memories have been realized using fully compensated antiferromagnetic metals. Here we demonstrate a multiple-stable memory device in epitaxial MnTe, an antiferromagnetic counterpart of common II–VI semiconductors. Favourable micromagnetic characteristics of MnTe allow us to demonstrate a smoothly varying zero-field antiferromagnetic anisotropic magnetoresistance (AMR) with a harmonic angular dependence on the writing magnetic field angle, analogous to ferromagnets. The continuously varying AMR provides means for the electrical read-out of multiple-stable antiferromagnetic memory states, which we set by heat-assisted magneto-recording and by changing the writing field direction. The multiple stability in our memory is ascribed to different distributions of domains with the Ne´el vector aligned along one of the three magnetic easy axes. The robustness against strong magnetic field perturbations combined with the multiple stability of the magnetic memory states are unique properties of antiferromagnets.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (≤30 ns), excellent endurance (~10 12 cycles), stability (>10 6 s) and scalability (down to ~60 nm 2 ). In situ Raman and ultraviolet–visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Goswami, Sreetosh↗
DOE OSTI2019

Dynamical nonlinear memory capacitance in biomimetic membranes

Two-terminal memory elements, or memelements, capable of co-locating signal processing and memory via history-dependent reconfigurability at the nanoscale are vital for next-generation computing materials striving to match the brain’s efficiency and flexible cognitive capabilities. While memory resistors, or memristors, have been widely reported, other types of memelements remain underexplored or undiscovered. Here we report the first example of a volatile, voltage-controlled memcapacitor in which capacitive memory arises from reversible and hysteretic geometrical changes in a lipid bilayer that mimics the composition and structure of biomembranes. We demonstrate that the nonlinear dynamics and memory are governed by two implicitly-coupled, voltage-dependent state variables—membrane radius and thickness. Further, our system is capable of tuneable signal processing and learning via synapse-like, short-term capacitive plasticity. These findings will accelerate the development of low-energy, biomolecular neuromorphic memelements, which, in turn, could also serve as models to study capacitive memory and signal processing in neuronal membranes.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Embedding security into ferroelectric FET array via in situ memory operation

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

A scalable superconducting nanowire memory array with row–column addressing

Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm −2 . Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10 −5 . Here, we also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.

Electrical and electronic engineering↗
DOE OSTI2016

Dopaminergic inputs in the dentate gyrus direct the choice of memory encoding

Rewarding experiences are often well remembered, and such memory formation is known to be dependent on dopamine modulation of the neural substrates engaged in learning and memory; however, it is unknown how and where in the brain dopamine signals bias episodic memory toward preceding rather than subsequent events. Here we found that photostimulation of channelrhodopsin-2–expressing dopaminergic fibers in the dentate gyrus induced a long-term depression of cortical inputs, diminished theta oscillations, and impaired subsequent contextual learning. Computational modeling based on this dopamine modulation indicated an asymmetric association of events occurring before and after reward in memory tasks. In subsequent behavioral experiments, preexposure to a natural reward suppressed hippocampus-dependent memory formation, with an effective time window consistent with the duration of dopamine-induced changes of dentate activity. Altogether, our results suggest a mechanism by which dopamine enables the hippocampus to encode memory with reduced interference from subsequent experience.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2018

Differential Age Effects of Transcranial Direct Current Stimulation on Associative Memory

Abstract Objectives Older adults experience associative memory deficits relative to younger adults (Old & Naveh-Benjamin, 2008). The aim of this study was to test the effect of transcranial direct current stimulation (tDCS) on face-name associative memory in older and younger adults. Method Experimenters applied active (1.5 mA) or sham (0.1 mA) stimulation with the anode placed over the left dorsolateral prefrontal cortex (dlPFC) during a face-name encoding task, and measured both cued recall and recognition performance. Participants completed memory tests immediately after stimulation and after a 24-h delay to examine both immediate and delayed stimulation effects on memory. Results Results showed improved face-name associative memory performance for both recall and recognition measures, but only for younger adults, whereas there was no difference between active and sham stimulation for older adults. For younger adults, stimulation-induced memory improvements persisted after a 24-h delay, suggesting delayed effects of tDCS after a consolidation period. Discussion Although effective in younger adults, these results suggest that older adults may be resistant to this intervention, at least under the stimulation parameters used in the current study. This finding is inconsistent with a commonly seen trend, where tDCS effects on cognition are larger in older than younger adults.

Leach, Ryan C.↗
DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗
DOE OSTI2017

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPU for efficient 3D rendering.

Innovative hardware/software co-design↗
DOE OSTI2024

Distributed-Memory Sparse Deep Neural Network Inference Using Global Arrays

Partitioned Global Address Space (PGAS) models exhibit tremendous promise in developing efficient and productive distributed-memory parallel applications. They have been used extensively in scientific computations due to conveniently offering a ``shared-memory''-like model and convenient interfaces that separate communication with synchronization. Traditionally, PGAS communication models have been applied to dense/contiguously distributed data, but most modern applications depict varied levels of sparsity. Existing PGAS models require certain adaptations to support distributed sparse computations, since associated computations often require matrix arithmetic, in addition to data movement. The Global Arrays toolkit from Pacific Northwest National Laboratory (PNNL) is one of the earliest PGAS models to combine one-sided data communication and distributed matrix operations and is still used in the popular NWChem quantum chemistry suite. Recently, we have expanded the Global Arrays toolkit to support common sparse operations, like sparse matrix-dense matrix multiplies (SpMM), sparse matrix-sparse matrix multiplication (SpGEMM) and Sampled Dense-Dense Matrix Multiplication (SDDMM). As it turns out, these operations are the bedrock of sparse Deep Learning (DL); sparse deep neural networks and Graph Neural Networks (GNNs) have gained increasing attention recently in achieving speedups on training and inference with reduced memory footprints. Unlike scientific applications in High Performance Computing (HPC), modern (distributed-memory capable) DL toolkits often rely on non-standardized and closed-source vendor software optimizations, creating challenges in software-hardware co-design at scale. Our goal is to support a variety of distributed-memory sparse matrix operations and helper functions in the newly created Sparse Global Arrays (SGA), such that it is possible to build portable and productive Machine Learning scenarios for algorithm/software and hardware codesign purposes. Contemporary data-parallel schemes for training/inference are undergoing a major overhaul since model replication limits scalability and causes resource inefficiencies. As such, we have adopted tensor parallelism in decomposing the model and inputs, to mitigate memory issues. Current implementation is built on top of MPI and uses CPUs to maximize the portability across the platforms.

Distributed computing, machine learning↗
DOE OSTI2025

IRIS-MEMFLOW: Data Flow-Enabled Portable Memory Orchestration in IRIS Runtime for Diverse Heterogeneity

Task-based programming models and execution paradigms provide a means to decompose a computation by expressing it as a graph in which each node represents a specific computation operating on memory objects and the edges define the dependencies in the execution flow. In this execution model, independent nodes in the graph can be executed concurrently in different computing devices, making it suitable for heterogeneous systems in which computing devices with different architectures coexist. However, careful memory orchestration across heterogeneous devices is needed because copies of the same memory object may reside in multiple devices during execution. Manually ensuring such an orchestration is quite challenging. Not only must an application developer guard against race conditions, but they must also optimize data movement between the host and devices because unnecessary data movement significantly impacts performance. To mitigate these challenges, we enhance the IRIS heterogeneous runtime and introduce IRIS-MEMFLOW–a data flow–enabled portable memory abstraction for seamlessly orchestrating memory in diverse heterogeneous computing environments. By using data-flow analysis, IRIS-MEMFLOW guards against race conditions while multiple heterogeneous devices access memory objects. IRIS-MEMFLOW also optimizes data movement between the host and devices without manual intervention. As a result, IRIS provides improved programming productivity, performance, and portability for multidevice heterogeneous executions in high-performance computing and cloud systems that run diverse architectures from different vendors. The efficacy of IRIS-MEMFLOW is evaluated through experiments that show its capability in terms of programming productivity, multidevice heterogeneity, portability, and low overhead versus the state of the art.

Monil, M. A. H. [ORNL] (ORCID:0000000334194037)↗
DOE OSTI2024

Picasso: Memory-Efficient Graph Coloring Using Palettes With Applications in Quantum Computing

A coloring of a graph is an assignment of colors to vertices such that no two neighboring vertices have the same color. The need for memory-efficient coloring algorithms is motivated by their application in computing clique partitions of graphs arising in quantum computations where the objective is to map a large set of Pauli strings into a compact set of unitaries. We present Picasso, a randomized memory-efficient iterative parallel graph coloring algorithm with theoretical sublinear space guarantees under practical assumptions. The parameters of our algorithm provide a trade-off between coloring quality and resource consumption. To assist the user, we also propose a machine learning model to predict the coloring algorithm’s parameters considering these trade-offs. We provide a sequential and a parallel implementation of the proposed algorithm. We perform an experimental evaluation on a 64-core AMD CPU equipped with 512 GB of memory and an Nvidia A100 GPU with 40GB of memory. For a small dataset where existing coloring algorithms can be executed within the 512 GB memory budget, we show up to 68× memory savings. On massive datasets we demonstrate that GPU-accelerated Picasso can process inputs with 49.5× more Pauli strings (vertex set in our graph) and 2,478× more edges than state-of-the-art parallel approaches.

artificial intelligence, quantum computing↗
DOE OSTI2015

Opportunities for nonvolatile memory systems in extreme-scale high-performance computing

For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integrate these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. In addition, current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2018

Performance Assessment of Emerging Memories Through FPGA Emulation

Emerging memory technologies offer the prospect of large capacity, high bandwidth, and a range of access latencies ranging from DRAM-like to SSD-like. In this paper, we evaluate the performance of parallel applications on CPUs whose main memories sweep a wide range of latencies within a bandwidth cap. We use an FPGA emulator, the logic in memory emulator (LiME) to accelerate evaluation. The LiME framework uses a multiprocessor system on chip (MPSoC) combining multicore CPU, integrated memory controller, and FPGA fabric, and enables emulation orders of magnitude faster than software simulation. This work highlights the performance impact of higher latency on concurrent applications and identifies conditions under which future high latency memories can effectively be used as main memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Shifting Between Compute and Memory Bounds: A Compression-Enabled Roofline Model

In the evolving landscape of high-performance computing, especially to fight the end of Moore’s Law and Dennard’s Scaling, the ability to shift between compute-bound and memory-bound states is critical for enhancing adaptability and flexibility to diverse system and domain-specific architectures. Such capability is vital for optimizing performance across distinguished hardware configurations, such as accelerators, memory hierarchies, and cache systems. Despite that ad hoc optimization techniques, such as compressed/approximate computation, have been enabled for compute-/data-intensive computing for improved performance in distinct hardware settings, there lacks an understanding of 1) the rational behind performance improvement; 2) capability of different optimizations; 3) what optimization to respond to specific computational and memory demands. This work proposes a compression-enabled roofline model to facilitate this adaptability with data compression techniques to balance and transform between computational and memory demands. This model enables applications to adjust in response to the specific strengths and limitations of the underlying hardware and system to optimize resource utilization. The effectiveness of this approach is demonstrated with matrix multiplication kernels on different input sizes, with turning on/off various compression techniques, including 1) low-precision floating point; 2) sparse matrix formulation; and 3) compressed arrays with ZFP. By reducing memory transfer volumes and cache misses and increasing data locality and computational intensity through compression, the specific roofline model can transform between compute and memory bounds to align more efficiently with system capabilities. This advancement not only improves overall performance but also maximizes adaptability in diverse computing environments.

Naraparaju, Ramasoumya [University of Washington]↗
DOE OSTI2021

Single-node Partitioned-Memory for Huge Graph Analytics: Cost and Performance Trade-offs

Nonvolatile memory NVDIMMs, available as Intel Optane, are less expensive than DRAM and bring large byte-addressable storage within reach to many applications. Evaluations on graph analytics have shown promising performance only when DRAM is used as a hardware cache (Memory mode). An open question is whether graph applications can exploit Optane and DRAM directly (AppDirect mode) and achieving better-than-DRAM average bandwidth and run times. We evaluate Optane as a volatile pool on two large-scale graph applications with very different computational patterns, Grappolo and Ripples. We show that AppDirect mode can deliver better-than-DRAM performance, by allocating data structures to Optane and DRAM according to their access characteristics, resulting in higher average memory bandwidth and lower average latency. Memory mode provides DRAM-competitive performance with capacity equal to persistent memory. We demonstrate occasional 4x improvement using the latest AppDirect option and frequently observe competitive performance between Optane AppDirect Memory modes and DRAM.

Ghosh, Sayan↗
DOE OSTI2022

MemLeap GPU Memory Profiler

MemLeap is a GPU Memory Profiler built atop Nvbit (NVidia Binary Instrumentation Tool) framework. It analyzes memory accesses to memory objects in GPU memory, including Unified Memory, to optimize memory usage and reveal performance bottlenecks.

Peng, Bo↗