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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Towards Automated Generation of Chiplet-Based Systems

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application- Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a high-level frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This talk will discuss ongoing work on the SODA synthesizer to enable no-human-in-the-loop generation and design space exploration of the chiplets for highly specialized artificial intelligence accelerators. Connecting these highly specialized chiplets to general-purpose cores or programmable accelerators will allow to quickly deploy autonomous systems for scientific discovery.

Limaye, Ankur M.↗
DOE OSTI2024

Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Monolithic integration of optical waveguides with metal routing layers

A photonic integrated circuit and a method for its manufacture are provided. In an embodiment, an intermetal dielectric layer, for example, a silicon oxide layer, is contiguous between an upper metal layer and a lower metal layer on a substrate. One or more waveguides having top and bottom faces are formed in respective waveguide layers within the intermetal dielectric layer between the upper and lower metal layers. There is a distance of at least 600 nm from the upper metal layer to the top face of the uppermost of the several waveguides. There is a distance of at least 600 nm from the lower metal layer to the bottom face of the lowermost of the several waveguides. The waveguides are formed of silicon nitride for longer wavelengths and alumina for shorter wavelengths. These dimensions and materials are favorable for CMOS processing, among other things.

Gehl, Michael↗
DOE OSTI2024

Preventing stent failure using adaptive shear responsive endovascular implant

A stent apparatus, system, and method that senses wall shear stress by measuring fluid flow at localized areas within the stent, that processes measured information through an integrated circuit, and selectively sends power to mechanically controllable stent surfaces which results in localized geometric changes. In various embodiments the stent apparatus, system, and method sends data to outside the body in real time.

Mukerjee, Erik V.↗
DOE OSTI2024

Method and apparatus for providing thermal wear leveling

Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

Roberts, David A.↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Schulte, Jan-Frederik [Purdue U.] (ORCID:000000034↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2020

Printed circuit board for integrated LED driver

A light emitting diode (LED) module may include a direct current (DC) voltage node formed on a first layer. The DC voltage node may be configured to sink a first current. One or more devices may be formed on the first layer configured to provide a second current to one or more LEDs. A device of the one or more devices may carry a steep slope voltage waveform. A local shielding area may be formed in a second layer directly below the DC voltage node and the one or more devices. The local shielding area may include a substantially continuous area of conductive material. A conductive via may extend through one or more layers. The conductive via may electrically connect the DC voltage node and the local shielding area.

Song, Zhihua↗
DOE OSTI2024

Modular DC circuit breaker with integrated energy storage for future DC networks

A T-breaker is an all-in-one solution for dc microgrid fault protection, power flow control, and power quality improvement. A T-breaker features a modular multilevel “T” structure with integrated energy storage devices. The two horizontal arms of the T-breaker realize fault current breaking, load voltage compensation, and power flow control; and the vertical arm of the T-breaker realizes shunt compensation. The configuration provides excellent voltage scalability and relaxes the requirements on the switching signal synchronization during fault transients. The local energy storage in sub-modules eases the fault energy dissipation requirement placed on the traditionally-adopted surge arrestors. The modular multilevel structure also offers immense control flexibility for all types of targeted functions of the provided T-breaker.

Wang, Jin↗
DOE OSTI2020

A Modular Integration Design of LCL Circuit Featuring Field Enhancement and Misalignment Tolerance for Wireless EV Charging

One of the major challenges of high-order wireless charging circuit is to reduce the system volume and cost induced by its additional components. Based on an LCL-S circuit, this paper proposes a modular integration design, in which an identical compensation inductor and transmitter are closely coupled. A new compensation method is derived to enable zero phase angle (ZPA) and constant current (CC) output. Identical currents are fed into the same reference terminals of both inductors to enable transmission field enhancement and to eliminate reactive power flow between the inductors. A misalignment tolerant coil is used to improve the output power stability under random parking imperfection. The proposed integration design achieves enhanced transmission capacity. Experiments are carried out to verify the proposed design.

Zhang, Pengcheng↗
DOE OSTI2020

Loop Antennas for Use On/Off Ground Planes

Many applications benefit from the ability of an RFID tag to operate both on and off a conducting ground plane. This paper presents an electrically small loop antenna at 433 MHz that passively maintains its free-space tune and match when located a certain distance away from a large conducting ground plane. The design achieves this using a single radiation mechanism (that of a loop) in both environments without the use of a ground plane or EBG/AMC structure. An equivalent circuit model is developed that explains the dual-environment behavior and shows that the geometry balances inductive and capacitive parasitics introduced by the ground plane such that the free-space loop reactance, and thus resonant frequency, does not change. A design equation for balancing the inductive and capacitive parasitic effects is derived. Finally, experimental data showing the design eliminates ground plane detuning in practice is presented. The design is suitable for active, “hard” RFID tag applications.

42 ENGINEERING↗
DOE OSTI2022

The ultrafast pixel array camera system and its applications in high energy density physics

Diagnostics in high energy density physics, shock physics, and related fields are primarily driven by a need to record rapidly time-evolving signals in single-shot events. These measurements are often limited by channel count and signal degradation issues on cable links between the detector and digitizer. Here we present the Ultrafast Pixel Array Camera (UPAC), a compact and flexible detector readout system with 32 waveform-recording channels at up to 10 Gsample/s and 1.8 GHz analog bandwidth. The compact footprint allows the UPAC to be directly embedded in the detector environment. A key enabling technology is the PSEC4A chip, an eight-channel switch-capacitor array sampling device with up to 1056 samples/channel. The UPAC system includes a high-density input connector that can plug directly into an application-specific detector board, programmable control, and serial readout, with less than 5 W of power consumption in full operation. We present the UPAC design and characterization, including a measured timing resolution of ~20 ps or better on acquisitions of sub-nanosecond pulses with minimal system calibrations. Example applications of the UPAC are also shown to demonstrate operation of a solid-state streak camera, an ultrafast imaging array, and a neutron time-of-flight spectrometer.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Real-time Condition Monitoring of Power Modules in Grid-tied Power Converter

This paper proposes and demonstrates a real-time condition monitoring method using gate driver integrated sensing circuits and sensor fusion algorithms. Power device on-state voltage (VDSon) measurement and junction temperature (Tj) sensing circuits with high noise immunity are built and integrated into an adaptive gate driver circuit for power modules. Considering the inherently noisy measurement environment of power converters, VDSon together with several other measurements are fused together to provide accurate descriptions of the stress and degradation of each power device. Furthermore, the gate driver circuit can actively control the turn-on gate voltage (VGSon) for each device based on the stress and degradation state. The proposed sensing circuits and power device condition assessment algorithms are implemented in a 75 KVA grid-tied power converter. This paper focuses on the sensing circuits hardware designs and testing in grid-tied power converter prototype and device stress index generation. More comprehensive results on the device state of health index generation will be presented in future work.

Fan, Junchong↗
DOE OSTI2022

An Innovative Circuit Breaker for Renewable Power Grids

A key step towards a carbon-neutral future could be reached through dispersed power grids, featuring networks of local-scale renewable energy and battery storage plants. To prevent these power grids from damaging themselves and their surroundings when electrical faults arise, they must be integrated with ‘circuit breakers’, which temporarily interrupt the current flowing through them. However, currently available circuit breakers cannot handle the medium-voltage direct currents best suited for these grids. Through an innovative new circuit breaker design, Steve Schmalz and his colleagues at Eaton Corporation, the Illinois Institute of Technology (IIT), Virginia Tech and the National Energy Technology Laboratory (NETL), hope that this challenge will soon be overcome.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Large-scale integration of artificial atoms in hybrid photonic circuits

A central challenge in developing quantum computers and long-range quantum networks is the distribution of entanglement across many individually controllable qubits. Colour centres in diamond have emerged as leading solid-state ‘artificial atom’ qubits because they enable on-demand remote entanglement, coherent control of over ten ancillae qubits with minute-long coherence times and memory-enhanced quantum communication. A critical next step is to integrate large numbers of artificial atoms with photonic architectures to enable large-scale quantum information processing systems. So far, these efforts have been stymied by qubit inhomogeneities, low device yield and complex device requirements. Here we introduce a process for the high-yield heterogeneous integration of ‘quantum microchiplets’—diamond waveguide arrays containing highly coherent colour centres—on a photonic integrated circuit (PIC). We use this process to realize a 128-channel, defect-free array of germanium-vacancy and silicon-vacancy colour centres in an aluminium nitride PIC. Photoluminescence spectroscopy reveals long-term, stable and narrow average optical linewidths of 54 megahertz (146 megahertz) for germanium-vacancy (silicon-vacancy) emitters, close to the lifetime-limited linewidth of 32 megahertz (93 megahertz). We show that inhomogeneities of individual colour centre optical transitions can be compensated in situ by integrated tuning over 50 gigahertz without linewidth degradation. The ability to assemble large numbers of nearly indistinguishable and tunable artificial atoms into phase-stable PICs marks a key step towards multiplexed quantum repeaters and general-purpose quantum processors

36 MATERIALS SCIENCE↗