Digital Application Specific Integrated Circuit Design
Single radiation effects can be transient and static. The charge collected from radiation has a prompt (drift) and a slow (diffusion) component. This current spike causes disparate results: SEU, SET, SEB, MBU, and more. A system level SEE mitigation technique, used to overcome, is the triple module redundancy (TMR). TMR for system Verilog (TMR4SV), written in Python, is the first step towards design IP triplication. It allows various triplication methods for flip flops, clocks, and logic.