New York City Transportation & Infrastructure: Assessing Urban Heat Island Effects at Bus Stops in New York City to Support Cooling Interventions
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Thomas Schindelman↗
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Results for “bus”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Dynamic Response Comparison of Dual-Wound and Single-Wound Machines in Multi-Bus Power System Architectures.
Abstract not provided.
Rashkin, Lee Joshua↗
A High-Fidelity Electromagnetic Transient Model of Inverter-based Resources Integrated to an IEEE-9 Bus System for Benchmarking Studies
An inverter-based resource (IBR) is a source of electricity that is asynchronously connected to the electrical grid via an electronic power converter. These power sources lack the intrinsic behaviors of the standard power plants, presenting specific challenges to system stability. These power sources lack the intrinsic behaviors of the standards power plants and their features are almost entirely defined by the control strategy used on them, presenting specific challenges to system stability as their penetration increases into the already fragile Bulk Power System (BPS). Utilizing renewable energy has a great upside but the electrical industry needs to understand the requirements like performing electromagnetic transient (EMT) simulation studies in planning and/or in interconnection studies. This paper presents the development of a high-fidelity EMT model based on commercial equipment and field parameters, which at the same time aims to study the increasing penetration of IBRs and their impact on the actual BPS. The open-source EMT model developed will be a benchmarking example that can be used to evaluate algorithms in the power grid (including evaluating grid-forming controls, power system monitoring and operation, etc.).
Martinez Montejano, Misael↗
Moving target defense for a serial communications system
A moving target defense scheme for a serial communications system is disclosed herein. A bus controller generates and broadcasts a nonce to remote terminals over a bus. The bus controller and the remote terminals generate a randomized sequence based upon the nonce and a shared secret that is shared between the bus controller and the remote terminals. The bus controller broadcasts first messages over the bus on first addresses that are derived from first portions of the randomized sequence. The remote terminals listen for the first messages that are broadcast over the bus on the first addresses. The bus controller broadcasts a shift message that causes the remote terminals to listen for second messages that are broadcast over the bus on second addresses that are derived from second portions of the randomized sequence.
Jenkins, Christipher D.↗
Application of new electro-optic technology to Space Station Freedom data management system
A low risk design methodology to permit the local bus structures to support increased data carrying capacities and to speed messages and data flow between nodes or stations on the Space Station Freedom Data Management System in anticipation of growing requirements was evaluated and recommended. The recommended design employs a collateral fiber optic technique that follows a NATO avionic standard that is developed, tested, and available. Application of this process will permit a potential 25 fold increase in data transfer performance on the local wire bus network with a fiber optic network, maintaining the functionality of the low-speed bus and supporting all of the redundant transmission and fault detection capabilities designed into the existing system. The application of wavelength division multiplexing (WDM) technology to both the local data bus and global data bus segments of the Data Management System to support anticipated additional highspeed data transmission requirements was also examined. Techniques were examined to provide a dual wavelength implementation of the fiber optic collateral networks. This dual wavelength implementation would permit each local bus to support two simultaneous high-speed transfers on the same fiber optic bus structure and operate within the limits of the existing protocol standard. A second WDM study examined the use of spectral sliced technology to provide a fourfold increase in the Fiber Distributed Data Interface (FDDI) global bus networks without requiring modifications to the existing installed cable plant. Computer simulations presented indicated that this data rate improvement can be achieved with commercially available optical components.
Husbands, C. R.↗
Modeling and mitigating airborne pathogen risk factors in school buses
Computational fluid dynamics (CFD) models were developed to simulate the impact of different ventilation scenarios on airborne exposure risks in a 72-passenger school bus. Here, scenarios and factors that were investigated included a moving vs. stationary bus, impacts of a heating unit within the bus, and impacts of alternative ventilation scenarios with different combinations of openings (e.g., windows, door, emergency hatch). Results of the simulations showed that when the bus was stationary, use of the heater increased receptor concentrations unless there was another opening. When the bus was moving, simulations with at least two sets of openings separated from each other in the forward and aft directions produced a through-flow condition that reduced concentrations via dilution from outside air by a factor of ten or more. A single opening in a moving bus generally increased concentrations throughout the cabin due to increased mixing with minimal ventilation. The cumulative exposure risk (time-averaged concentrations) was found to be inversely correlated to the air exchange rate. Stationary and moving-bus scenarios that yielded above ~20 air changes per hour resulted in the lowest cumulative exposures. Recommendations from this study were implemented in new safety and operating procedures by the Albuquerque Public Schools Transportation Center.
60 APPLIED LIFE SCIENCES↗
Modular Cooling Components
Three modular heat-transfer components designed for use together or separately. Simple mechanical connections facilitate assembly of these and related heat-transfer components into cooling systems of various configurations, such as to cool laboratory equipment rearranged for different experiments. Components are clamp-on cold plate, cold plate attached to flexible heat pipe, and thermal-bus receptacle. Clamp-on cold plate moved to any convenient location for attachment of equipment cooled by it, then clamped onto thermal bus. Heat from equipment conducted through plate and into coolant. Thermal-bus receptacle integral with thermal bus. Includes part of thermal bus to which clamp-on cold plate attached, plus tapered socket into which condenser end of flexible heat pipe plugged. Thermal-bus receptacle includes heat-pipe wick structure using coolant in bus to enhance transfer of heat from cold plate.
Eastman, G. Yale↗
Programmable DMA controller
In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.
Hendry, David F.↗
Cluster Inter-Spacecraft Communications
A document describes a radio communication system being developed for exchanging data and sharing data-processing capabilities among spacecraft flying in formation. The system would establish a high-speed, low-latency, deterministic loop communication path connecting all the spacecraft in a cluster. The system would be a wireless version of a ring bus that complies with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus enhancement to the IEEE standard developed at NASA's Jet Propulsion Laboratory). Every spacecraft in the cluster would be equipped with a ring-bus radio transceiver. The identity of a spacecraft would be established upon connection into the ring bus, and the spacecraft could be at any location in the ring communication sequence. In the event of failure of a spacecraft, the ring bus would reconfigure itself, bypassing a failed spacecraft. Similarly, the ring bus would reconfigure itself to accommodate a spacecraft newly added to the cluster or newly enabled or re-enabled. Thus, the ring bus would be scalable and robust. Reliability could be increased by launching, into the cluster, spare spacecraft to be activated in the event of failure of other spacecraft.
Cox, Brian↗
Smart Power Supply for Battery-Powered Systems
A power supply for battery-powered systems has been designed with an embedded controller that is capable of monitoring and maintaining batteries, charging hardware, while maintaining output power. The power supply is primarily designed for rovers and other remote science and engineering vehicles, but it can be used in any battery alone, or battery and charging source applications. The supply can function autonomously, or can be connected to a host processor through a serial communications link. It can be programmed a priori or on the fly to return current and voltage readings to a host. It has two output power busses: a constant 24-V direct current nominal bus, and a programmable bus for output from approximately 24 up to approximately 50 V. The programmable bus voltage level, and its output power limit, can be changed on the fly as well. The power supply also offers options to reduce the programmable bus to 24 V when the set power limit is reached, limiting output power in the case of a system fault detected in the system. The smart power supply is based on an embedded 8051-type single-chip microcontroller. This choice was made in that a credible progression to flight (radiation hard, high reliability) can be assumed as many 8051 processors or gate arrays capable of accepting 8051-type core presently exist and will continue to do so for some time. To solve the problem of centralized control, this innovation moves an embedded microcontroller to the power supply and assigns it the task of overseeing the operation and charging of the power supply assets. This embedded processor is connected to the application central processor via a serial data link such that the central processor can request updates of various parameters within the supply, such as battery current, bus voltage, remaining power in battery estimations, etc. This supply has a direct connection to the battery bus for common (quiescent) power application. Because components from multiple vendors may have differing power needs, this supply also has a secondary power bus, which can be programmed a priori or on-the-fly to boost the primary battery voltage level from 24 to 50 V to accommodate various loads as they are brought on line. Through voltage and current monitoring, the device can also shield the charging source from overloads, keep it within safe operating modes, and can meter available power to the application and maintain safe operations.
Krasowski, Michael J.↗
Four-Channel PC/104 MIL-STD-1553 Circuit Board
The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.
Cox, Gary L.↗
Electrical Substation Configuration Effect on Substation Reliability
The nation’s electrical grid must be reliable because of its critical role in the economy, defense, and security of the nation. Many common tasks and industrial operations rely on proper electrical power distribution. In the design of new bus systems or evaluation of existing bus systems, the type of bus configuration affects the risk, reliability, maintenance, and cost of the system. This work utilizes Systems Analysis Programs for Hands-on Integrated Reliability Evaluations (SAPHIRE) to perform a probabilistic risk assessment (PRA) based sensitivity study on the reliability of substations with differing bus configurations. This study examines single bus, main and transfer, breaker and a half, double bus/double breaker, and ring bus configurations applied to busses of varying number of lines. The case variances, methods, and rankings presented can provide a guide for bus configuration for future electrical grid design and analysis.
24 POWER TRANSMISSION AND DISTRIBUTION↗
From CAN to ROS: A Monitoring and Data Recording Bridge
The Controller Area Network (CAN) bus protocol is used in modern vehicles for sharing messages between several control units within a vehicle. CAN bus messages are encoded with unknown scheme and decoding these messages provide unlimited access to valuable information that is used in many autonomous vehicles applications. This paper proposes a ROS based package (CAN-to-ROS) for monitoring, recording, and real-time and offline decoding of CAN bus messages. The package is developed in the ROS framework to add modularity and ease of integration with other software, and it is written in C++ to guarantee speed of the execution during run-time. For realtime decoding of CAN bus data, CAN-to-ROS package used in conjunction with other library called Libpanda that provide access to CAN bus message from a vehicle. The package was evaluated and tested on a Raspberry Pi with real CAN bus data from a Toyota RAV4. The results confirm the capabilities of CAN-to-ROS package and resulted in using the package in other research projects.
Elmadani, Safwan↗
Fault tolerant data management system
Described in detail are: (1) results obtained in modifying the onboard data management system software to a multiprocessor fault tolerant system; (2) a functional description of the prototype buffer I/O units; (3) description of modification to the ACADC and stimuli generating unit of the DTS; and (4) summaries and conclusions on techniques implemented in the rack and prototype buffers. Also documented is the work done in investigating techniques of high speed (5 Mbps) digital data transmission in the data bus environment. The application considered is a multiport data bus operating with the following constraints: no preferred stations; random bus access by all stations; all stations equally likely to source or sink data; no limit to the number of stations along the bus; no branching of the bus; and no restriction on station placement along the bus.
Gustin, W. M.↗
Digital Autonomous Terminal Access Communication (DATAC) system
In order to accommodate the increasing number of computerized subsystems aboard today's more fuel efficient aircraft, the Boeing Co. has developed the DATAC (Digital Autonomous Terminal Access Control) bus to minimize the need for point-to-point wiring to interconnect these various systems, thereby reducing total aircraft weight and maintaining an economical flight configuration. The DATAC bus is essentially a local area network providing interconnections for any of the flight management and control systems aboard the aircraft. The task of developing a Bus Monitor Unit was broken down into four subtasks: (1) providing a hardware interface between the DATAC bus and the Z8000-based microcomputer system to be used as the bus monitor; (2) establishing a communication link between the Z8000 system and a CP/M-based computer system; (3) generation of data reduction and display software to output data to the console device; and (4) development of a DATAC Terminal Simulator to facilitate testing of the hardware and software which transfer data between the DATAC's bus and the operator's console in a near real time environment. These tasks are briefly discussed.
Novacki, Stanley M., III↗
Fault-tolerant processing system
A fault-tolerant, fiber optic interconnect, or backplane, which serves as a via for data transfer between modules. Fault tolerance algorithms are embedded in the backplane by dividing the backplane into a read bus and a write bus and placing a redundancy management unit (RMU) between the read bus and the write bus so that all data transmitted by the write bus is subjected to the fault tolerance algorithms before the data is passed for distribution to the read bus. The RMU provides both backplane control and fault tolerance.
Palumbo, Daniel L.↗
Multiple output power supply circuit for an ion engine with shared upper inverter
A power supply circuit for an ion engine suitable for a spacecraft is coupled to a bus having a bus input and a bus return. The power supply circuit has a first primary winding of a first transformer. An upper inverter circuit is coupled to the bus input and the first primary winding. The power supply circuit further includes a first lower inverter circuit coupled to the bus return and the first primary winding. The second primary winding of a second transformer is coupled to the upper inverter circuit. A second lower inverter circuit is coupled to the bus return and the second primary winding.
Cardwell, Jr., Gilbert I.↗
FPGA for Power Control of MSL Avionics
A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.
Wang, Duo↗