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At least 343 records · Page 19

All sources NASA NTRS DOE OSTI

NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗

NASA NTRS2010

Reconfigurable Fault Tolerance for FPGAs

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Shuler, Robert, Jr.↗

NASA NTRS2010

Reconfigurable structure

A reconfigurable structure includes a plurality of selectively extensible and retractable limbs, at least one node pivotably receiving respective ends of at least two limbs, and an actuator associated with each limb for extending and retracting the limb. The structure may further include an addressable module associated with each actuator to control the actuator.

Curtis, Steven A.↗

NASA NTRS2005

Printed Antennas Made Reconfigurable by Use of MEMS Switches

A class of reconfigurable microwave antennas now undergoing development comprise fairly conventional printed-circuit feed elements and radiating patches integrated with novel switches containing actuators of the microelectromechanical systems (MEMS) type. In comparison with solid-state electronic control devices incorporated into some prior printed microwave antennas, the MEMS-based switches in these antennas impose lower insertion losses and consume less power. Because the radio-frequency responses of the MEMS switches are more nearly linear, they introduce less signal distortion. In addition, construction and operation are simplified because only a single DC bias line is needed to control each MEMS actuator.

Simons, Rainee N.↗

NASA NTRS2011

Flexible, reconfigurable, power efficient transmitter and method

A flexible, reconfigurable, power efficient transmitter device and method is provided. In one embodiment, the method includes receiving outbound data and determining a mode of operation. When operating in a first mode the method may include modulation mapping the outbound data according a modulation scheme to provide first modulation mapped digital data, converting the first modulation mapped digital data to an analog signal that comprises an intermediate frequency (IF) analog signal, upconverting the IF analog signal to produce a first modulated radio frequency (RF) signal based on a local oscillator signal, amplifying the first RF modulated signal to produce a first RF output signal, and outputting the first RF output signal via an isolator. In a second mode of operation method may include modulation mapping the outbound data according a modulation scheme to provide second modulation mapped digital data, converting the second modulation mapped digital data to a first digital baseband signal, conditioning the first digital baseband signal to provide a first analog baseband signal, modulating one or more carriers with the first analog baseband signal to produce a second modulated RF signal based on a local oscillator signal, amplifying the second RF modulated signal to produce a second RF output signal, and outputting the second RF output signal via the isolator. The digital baseband signal may comprise an in-phase (I) digital baseband signal and a quadrature (Q) baseband signal.

Bishop, James W.↗

NASA NTRS2011

Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications

A technique was developed to provide a reconfigurable high-precision micro - wave electrical phase delay for resonators and phase shifters. The invention employs multiple branches of transmission lines with open-ended or ground-ended terminations as configurable bits or digits. This technique minimizes the errors due to limited precision of switching devices. In addition, the proposed linear analytical approach significantly produces a much simpler design than that of other prior inventions at the time of this reporting. Microwave components such as filters, phase delay elements, or resonators require a method that can accurately adjust their frequency responses. Most tuning techniques offer very wide frequency tuning range; however, it is often difficult and expensive to tune their response in a very narrow operating frequency, especially when the tuning element reaches its minimum discrete step due to fabrication tolerances. The problem becomes worse as the operating frequency is in mm-wave frequency range (>26 GHz). The electrical tuning sensitivity of a microwave line is dependent on the position of the tuning element with respect to the reference termination. By placing this tuning element away from this reference with the main transmission line connecting the two elements together the sensitivity of the tuning element can change significantly. This concept can be used in the system that requires multiple tuning sensitivities. In this case, multiple tuning branches are superimposed in the main transmission line. The proposed invention allows the transmission-line electrical length to be accurately programmed using switching elements that have limited accuracy. The invention consists of multiple branches of transmission lines connected to discrete switching devices with open-ended terminations. They are used as discrete tuning elements. These elements are connected to the main microwave transmission line and are separated by a well-defined electrical degree spacing. Each branch is programmed to have different electrical degree sensitivity, such as a combination of discrete steps in each branch, which results in a reflective line with a unique effective phase response. To reduce the number of switching devices, it is desirable to program the devices in binary configuration where each branch represents one bit in the base-2 number system. This invention allows the transmission line electrical length to be tuned precisely with customizable sensitivity based on the known sensitivity of the base tuning circuit. The tuning resolution is dependent on the distance among tuning branches.

Hsieh, Wen-Ting↗

NASA NTRS2012

Dynamically Reconfigurable Systolic Array Accelerator

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Dasu, Aravind↗

NASA NTRS2011

Design, Development and Pre-Flight Testing of the Communications, Navigation, and Networking Reconfigurable Testbed (Connect) to Investigate Software Defined Radio Architecture on the International Space Station

The Communication Navigation and Networking Reconfigurable Testbed (CoNNeCT) is a NASA-sponsored mission, which will investigate the usage of Software Defined Radios (SDRs) as a multi-function communication system for space missions. A softwaredefined radio system is a communication system in which typical components of the system (e.g., modulators) are incorporated into software. The software-defined capability allows flexibility and experimentation in different modulation, coding and other parameters to understand their effects on performance. This flexibility builds inherent redundancy and flexibility into the system for improved operational efficiency, real-time changes to space missions and enhanced reliability/redundancy. The CoNNeCT Project is a collaboration between industrial radio providers and NASA. The industrial radio providers are providing the SDRs and NASA is designing, building and testing the entire flight system. The flight system will be integrated on the Express Logistics Carrier (ELC) on the International Space Station (ISS) after launch on the H-IIB Transfer Vehicle in 2012. This paper provides an overview of the technology research objectives, payload description, design challenges and pre-flight testing results.

Over, Ann P.↗

NASA NTRS2012

Operator Interface and Control Software for the Reconfigurable Surface System Tri-ATHLETE

Graphical operator interface methods have been developed for modular, reconfigurable articulated surface systems in general, and a specific instantiation thereof for JPL's Tri-ATHLETE. The All- Terrain Hex-Limbed Extra-Terrestrial Explorer Robot (ATHLETE) has six limbs with six kinematic degrees of freedom each. The core advancement of this work was the development of a novel set of algorithms for dynamically maintaining a reduced coordinate model of any connected assembly of robot modules.

Norris, Jeffrey S.↗

NASA NTRS2012

Expandable and reconfigurable instrument node arrays

An expandable and reconfigurable instrument node includes a feature detection means and a data processing portion in communication with the feature detection means, the data processing portion configured and disposed to process feature information. The instrument node further includes a phase locked loop (PLL) oscillator in communication with the data processing portion, the PLL oscillator configured and disposed to provide PLL information to the processing portion. The instrument node further includes a single tone transceiver and a pulse transceiver in communication with the PLL oscillator, the single tone transceiver configured and disposed to transmit or receive a single tone for phase correction of the PLL oscillator and the pulse transceiver configured and disposed to transmit and receive signals for phase correction of the PLL oscillator. The instrument node further includes a global positioning (GPA) receiver in communication with the processing portion, the GPS receiver configured and disposed to establish a global position of the instrument node.

Hilliard, Lawrence M.↗

NASA NTRS2014

Transformable and Reconfigurable Entry, Descent and Landing Systems and Methods

A deployable aerodynamic decelerator structure includes a ring member disposed along a central axis of the aerodynamic decelerator, a plurality of jointed rib members extending radially from the ring member and a flexible layer attached to the plurality of rib members. A deployment device is operable to reconfigure the flexible layer from a stowed configuration to a deployed configuration by movement of the rib members and a control device is operable to redirect a lift vector of the decelerator structure by changing an orientation of the flexible layer.

Fernandez, Ian M.↗

NASA NTRS2016

A Benefit Analysis of Infusing Wireless into Aircraft and Fleet Operations - Report to Seedling Project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled, Wireless Architecture (ECON)

We report on an examination of potential benefits of infusing wireless technologies into various areas of aircraft and airspace operations. The analysis is done in support of a NASA seedling project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled Wireless Architecture (ECON). The study has two objectives. First, we investigate one of the main benefit hypotheses of the ECON proposal: that the replacement of wired technologies with wireless would lead to significant weight reductions on an aircraft, among other benefits. Second, we advance a list of wireless technology applications and discuss their system benefits. With regard to the primary hypothesis, we conclude that the promise of weight reduction is premature. Specificity of the system domain and aircraft, criticality of components, reliability of wireless technologies, the weight of replacement or augmentation equipment, and the cost of infusion must all be taken into account among other considerations, to produce a reliable estimate of weight savings or increase.

Alexandrov, Natalia↗

NASA NTRS2016

Reconfigurable, Intelligently-Adaptive, Communication System, an SDR Platform

The Space Telecommunications Radio System (STRS) provides a common, consistent framework to abstract the application software from the radio platform hardware. STRS aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. The NASA Glenn Research Center (GRC) team made a software defined radio (SDR) platform STRS compliant by adding an STRS operating environment and a field programmable gate array (FPGA) wrapper, capable of implementing each of the platforms interfaces, as well as a test waveform to exercise those interfaces. This effort serves to provide a framework toward waveform development onto an STRS compliant platform to support future space communication systems for advanced exploration missions. The use of validated STRS compliant applications provides tested code with extensive documentation to potentially reduce risk, cost and e ort in development of space-deployable SDRs. This paper discusses the advantages of STRS, the integration of STRS onto a Reconfigurable, Intelligently-Adaptive, Communication System (RIACS) SDR platform, and the test waveform and wrapper development e orts. The paper emphasizes the infusion of the STRS Architecture onto the RIACS platform for potential use in next generation flight system SDRs for advanced exploration missions.

space communications↗

NASA NTRS2016

Reconfigurable, Intelligently-Adaptive, Communication System, an SDR Platform

The Space Telecommunications Radio System (STRS) provides a common, consistent framework to abstract the application software from the radio platform hardware. STRS aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. The Glenn Research Center (GRC) team made a software-defined radio (SDR) platform STRS compliant by adding an STRS operating environment and a field programmable gate array (FPGA) wrapper, capable of implementing each of the platforms interfaces, as well as a test waveform to exercise those interfaces. This effort serves to provide a framework toward waveform development on an STRS compliant platform to support future space communication systems for advanced exploration missions. Validated STRS compliant applications provided tested code with extensive documentation to potentially reduce risk, cost and efforts in development of space-deployable SDRs. This paper discusses the advantages of STRS, the integration of STRS onto a Reconfigurable, Intelligently-Adaptive, Communication System (RIACS) SDR platform, the sample waveform, and wrapper development efforts. The paper emphasizes the infusion of the STRS Architecture onto the RIACS platform for potential use in next generation SDRs for advance exploration missions.

space communications↗

NASA NTRS2017

Reconfigurable Drive Current System

A reconfigurable drive current system includes drive stages, each of which includes a high-side transistor and a low-side transistor in a totem pole configuration. A current monitor is coupled to an output of each drive stage. Input channels are provided to receive input signals. A processor is coupled to the input channels and to each current monitor for generating at least one drive signal using at least one of the input signals and current measured by at least one of the current monitors. A pulse width modulation generator is coupled to the processor and each drive stage for varying the drive signals as a function of time prior to being supplied to at least one of the drive stages.

Alhorn, Dean C.↗

NASA NTRS2017

Reconfigurable Wideband Circularly Polarized Stacked Square Patch Antenna for Cognitive Radios

An almost square patch, a square patch and a stacked square patch with corner truncation for circular polarization (CP) are researched and developed at X-band for cognitive radios. Experimental results indicate, first, that the impedance bandwidth of a CP almost square patch fed from the edge by a 50 ohm line is 1.70 percent and second, that of a CP square patch fed from the ground plane side by a surface launch connector is 1.87 percent. Third, the impedance bandwidth of a CP stacked square patch fed by a surface launch connector is 2.22 percent. The measured center frequency for the CP square patch fed by a surface launch connector without and with an identical stacked patch is 8.45 and 8.1017 GHz, respectively. By stacking a patch, separated by a fixed air gap of 0.254 mm, the center frequency is observed to shift by as much as 348.3 MHz. The shift in the center frequency can be exploited to reconfigure the operating frequency by mechanically increasing the air gap. The results indicate that a tuning bandwidth of about 100 MHz can be achieved when the distance of separation between the driven patch and the stacked patch is increased from its initial setting of 0.254 to 1.016 mm.

Cognitive↗

NASA NTRS2017

On-Orbit Reconfigurable Solar Array

In one or more embodiments, the present disclosure teaches a method for reconfiguring a solar array. The method involves providing, for the solar array, at least one string of solar cells. The method further involves deactivating at least a portion of at least one of the strings of solar cells of the solar array when power produced by the solar array reaches a maximum power allowance threshold. In addition, the method involves activating at least a portion of at least one of the strings of the solar cells in the solar array when the power produced by the solar array reaches a minimum power allowance threshold.

Levy, Robert K.↗

NASA NTRS2017

Reconfigurable Sensor Monitoring System

A reconfigurable sensor monitoring system includes software tunable filters, each of which is programmable to condition one type of analog signal. A processor coupled to the software tunable filters receives each type of analog signal so-conditioned.

Alhorn, Dean C.↗