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At least 343 records · Page 19

All sources NASA NTRS DOE OSTI

NASA NTRS1988

Development of an adaptive LDV signal processor

Recent attempts at realization of a frequency domain signal processor exhibit practical drawbacks such as manual gain, filter and sampling adjustments, and simplistic adaptations of frequency domain techniques. This paper introduces an adaptive LDV signal processor, one which requires no operator intervention under any circumstances by adapting dynamically to burst characteristics, while surpassing all previous techniques in range and accuracy.

Baker, Glenn D.↗

NASA NTRS1988

Remotely controllable real-time optical processor

An optical processor is provided which facilitates selection of any of a variety of patterns or images which are to be compared with a Fourier transform of a template image, wherein the processor can be constructed at low cost. One of the two images that are to be compared is formed by generating video signals representing the image and using those signals to drive a liquid crystal array through which light passes.

Hua-Kuang Liu↗

NASA NTRS1988

Frequency domain laser velocimeter signal processor

A laser velocimeter signal processor for measuring the signal frequency within a signal burst. The input signal is converted to digital by an ADC 16 and then shifted into shift registers 30 and 31. An automatic gain circuit 15 controls the gain of the input signal. A signal integration circuit 32 determines when a signal burst has been captured by the shift registers and then transfers the contents of the registers to data latches 33 and 34. The data in data latches 33 and 34 is processed by digital bandpass filters 57-63, square law detectors 64-70, burst counters 71-77 and signal processor 78 to determine the frequency of the signal within the captured signal burst.

James F Meyers↗

NASA NTRS1987

An optical processor for object recognition and tracking

The design and development of a miniaturized optical processor that performs real time image correlation are described. The optical correlator utilizes the Vander Lugt matched spatial filter technique. The correlation output, a focused beam of light, is imaged onto a CMOS photodetector array. In addition to performing target recognition, the device also tracks the target. The hardware, composed of optical and electro-optical components, occupies only 590 cu cm of volume. A complete correlator system would also include an input imaging lens. This optical processing system is compact, rugged, requires only 3.5 watts of operating power, and weighs less than 3 kg. It represents a major achievement in miniaturizing optical processors. When considered as a special-purpose processing unit, it is an attractive alternative to conventional digital image recognition processing. It is conceivable that the combined technology of both optical and ditital processing could result in a very advanced robot vision system.

Sloan, J.↗

NASA NTRS1989

Generic element processor (application to nonlinear analysis)

The focus here is on one aspect of the Computational Structural Mechanics (CSM) Testbed: finite element technology. The approach involves a Generic Element Processor: a command-driven, database-oriented software shell that facilitates introduction of new elements into the testbed. This shell features an element-independent corotational capability that upgrades linear elements to geometrically nonlinear analysis, and corrects the rigid-body errors that plague many contemporary plate and shell elements. Specific elements that have been implemented in the Testbed via this mechanism include the Assumed Natural-Coordinate Strain (ANS) shell elements, developed with Professor K. C. Park (University of Colorado, Boulder), a new class of curved hybrid shell elements, developed by Dr. David Kang of LPARL (formerly a student of Professor T. Pian), other shell and solid hybrid elements developed by NASA personnel, and recently a repackaged version of the workhorse shell element used in the traditional STAGS nonlinear shell analysis code. The presentation covers: (1) user and developer interfaces to the generic element processor, (2) an explanation of the built-in corotational option, (3) a description of some of the shell-elements currently implemented, and (4) application to sample nonlinear shell postbuckling problems.

Stanley, Gary↗

NASA NTRS1988

A compact implementation of a real time acousto-optic synthetic aperture radar processor

The architecture of a real-time acoustooptic synthetic aperture radar processor is reviewed and recent efforts to develop a compact processor are presented. It employs an acoustooptic device operated in the space integrating mode to compress the signal in range.

Shaik, Kamran↗

NASA NTRS1988

The design of an onboard digital Doppler processor for a spaceborne scatterometer

A digital Doppler processor, which will permit the Doppler center frequency of the measurement cell bandwidths to be adjusted to compensate for the effects of the earth's rotation, will be used in the next NASA spaceborn scatterometer known as NSCAT. The authors describe the design and genesis of the NSCAT digital Doppler processor and discusses the performance tradeoff issues that were evaluated during the design phase. In this FFT (fast Fourier transform)-based technique, computation of the adjustment to the cell center frequencies will be done onboard using an approximate expression for the Doppler shift of the cell center versus orbit time. This technique also permits modification of the parameters used to locate the radar-backscatter-coefficient measurement cells by ground command in response to orbit changes.

Long, David G.↗

NASA NTRS1988

The role of specialized processors in the NAS program - Retrospective/prospective

The Numerical Aerodynamic Simulation (NAS) Program was initiated by NASA to establish a national resource for scientific research and engineering applications of computational fluid dynamics. This paper examines the changing views of the roles of general purpose and special purpose processors in this program in response to changes in technology as well as changes in perceived needs. The time period covered extends from more than 10 years ago, through the present, and concludes with some speculative concepts for the future roles of specialized processors in the advanced NAS system.

Levin, Eugene↗

NASA NTRS1988

Application of the hypercube parallel processor to a large-scale moment method code

The applicability of a parallel computing architecture to the solution of a large-scale moment-method code is investigated. Specifically, the NEC (Numerical Electromagnetics Code) method-of-moments scattering program is implemented on a hypercube parallel processor. The accuracy and the increase in the speed of execution on this parallel architecture are demonstrated. The results show a very large reduction in execution time for large problems. The great potential of this parallel processor is shown for interactive solution of large NEC problems as well as other moment-method techniques such as the finite-element method.

Manshadi, Farzin↗

NASA NTRS1988

VLSI high speed packet processor

The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.

Grebowsky, Gerald J.↗

NASA NTRS1988

LARP - An adaptive LDV signal processor

Baker, Glenn D.↗

NASA NTRS1990

Frequency-Domain Signal Processor For Laser Velocimeter

Dynamic range and accuracy increased. New signal processor for laser-velocimeter (LV) applications overcomes major limitations of present signal processors. System requires no input-signal conditioning other than that provided by amplifiers; it operates in instantaneous mode at signal levels from bursts containing as few as 150 photons down to photon-resolved regime in averaging mode. Digital value of signal-burst frequency sent to external computer system for conversion to value of absolute frequency. Residual turbulence intensity 0.2 percent, with little dependence on signal-to-noise ratio.

Meyers, James F.↗

NASA NTRS1988

Scan line graphics generation on the massively parallel processor

Described here is how researchers implemented a scan line graphics generation algorithm on the Massively Parallel Processor (MPP). Pixels are computed in parallel and their results are applied to the Z buffer in large groups. To perform pixel value calculations, facilitate load balancing across the processors and apply the results to the Z buffer efficiently in parallel requires special virtual routing (sort computation) techniques developed by the author especially for use on single-instruction multiple-data (SIMD) architectures.

Dorband, John E.↗

NASA NTRS1990

Onboard processor technology review

The general need and requirements for the onboard embedded processors necessary to control and manipulate data in spacecraft systems are discussed. The current known requirements are reviewed from a user perspective, based on current practices in the spacecraft development process. The current capabilities of available processor technologies are then discussed, and these are projected to the generation of spacecraft computers currently under identified, funded development. An appraisal is provided for the current national developmental effort.

Benz, Harry F.↗

NASA NTRS1990

Effects of error sources on the parallelism of an optical matrix-vector processor

The error sources in a high accuracy optical matrix-vector processor are analyzed by numerical simulation in terms of their effects on the parallelism and speed of the processor. These effects are detailed for radices -2, -4 and -8. Radix -4 is shown to provide maximum parallel processing capabilities under the effects of the system's error sources. Processing speed is shown to be a function of matrix partitioning and the number of parallel processing channels. Consequently, radix -4 operation provides a higher processing speed than radix -2 and -8 for most matrix-vector multiplications when error source effects are considered.

Perlee, Caroline J.↗

NASA NTRS1990

Simultaneous multivelocity component laser Doppler velocimetry using one digital frequency processor

Digital frequency processing used in conjunction with optical frequency shifting is an ideal way to achieve simultaneous multivelocity component measurements in laser Doppler velocimetry. This becomes obvious once realized that multivelocity component information at different frequency offsets can be obtained directly from the composite frequency spectrum of a single-channel digital frequency processor. The approach has numerous advantages over the very popular approach of using a different laser wavelength, photodetector, and signal processor for each velocity component.

Johnson, D. A.↗

NASA NTRS1991

Programmable Maintenance Processor For XAIDS

Programmable maintenance processor (MAINT) made of commercially available integrated circuits. Autonomous one of four digital electronic processors in extended aircraft interrogation and display system (XAIDS). Developed for testing of system and application computer programs as well as for testing equipment. MAINT has independent terminal and printer interfaces and dedicated magnetic bubble memory storing system-testing sequences entered from terminal. Software for MAINT written in PLM86 programming language and broken into four separate modules.

Glover, Richard↗

NASA NTRS1990

A Byzantine resilient processor with an encoded fault-tolerant shared memory

The memory requirements for ultra-reliable computers are expected to increase due to future increases in mission functionality and operating-system requirements. This increase will have a negative effect on the reliability and cost of the system. Increased memory size will also reduce the ability to reintegrate a channel after a transient fault, since the time required to reintegrate a channel in a conventional fault-tolerant processor is dominated by memory realignment time. A Byzantine Resilient Fault-Tolerant Processor with Fault-Tolerant Shared Memory (FTP/FTSM) is presented as a solution to these problems. The FTSM uses an encoded memory system, which reduces the memory requirement by one-half compared to a conventional quad-FTP design. This increases the reliability and decreases the cost of the system. The realignment problem is also addressed by the FTSM. Because any single error is corrected upon a read from the FTSM, a faulty channel's corrupted memory does not need realignment before reintegration of the faulty channel. A combination of correct-on-access and background scrubbing is proposed to prevent the accumulation of transient errors in the memory. With a hardware-implemented scrubber, the scrubbing cycle time, and therefore the memory fault latency, can be upper-bounded at a small value. This technique increases the reliability of the memory system and facilitates validation of its reliability model.

Butler, Bryan↗