Circuits and circuit testing for spaceborne redundant digital systems Special technical report no. 3
Design and testing of majority logic redundancy for spaceborne and GSE digital systems
REDUNDANT SYSTEM↗
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Results for “Logic Design”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Study of advanced associative processor techniques Interim report
Design of magnetic memory and logic cell arrays for associative processor useful in spaceborne applications
Jauvtis, H. I.↗
Research in the effective implementation of guidance computers with large scale arrays Interim report
Functional logic character implementation in breadboard design of NASA modular computer
Burke, J. A.↗
Description of eight station radar near Havana, Illinois
A general description is given of the eight-station system at Havana which incorporated high-gain antennas and a powerful transmitter to reach faint meteors on the order of magnitude of plus 12. The station location, principle of system design, systems connections, transmitter, receivers, logics, range measurement, and recording are described.
Southworth, R. B.↗
Research in digital adaptive flight controllers
A design study of adaptive control logic suitable for implementation in modern airborne digital flight computers was conducted. Both explicit controllers which directly utilize parameter identification and implicit controllers which do not require identification were considered. Extensive analytical and simulation efforts resulted in the recommendation of two explicit digital adaptive flight controllers. Interface weighted least squares estimation procedures with control logic were developed using either optimal regulator theory or with control logic based upon single stage performance indices.
Kaufman, H.↗
Hardware additions to microprocessor architecture aid software development
An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.
Sievers, M. W.↗
A new design approach to achieve a minimum impulse limit cycle in the presence of significant measurement uncertainties
A new design was developed for the Space Shuttle Transition Phase Digital Autopilot to reduce the impact of large measurement uncertainties in the rate signal during attitude control. The signal source, which was dictated by early computer constraints, is characterized by large quantization, noise, bias, and transport lag which produce a measurement uncertainty larger than the minimum impulse rate change. To ensure convergence to a minimum impulse limit cycle, the design employed bias and transport lag compensation and a switching logic with hysteresis, rate deadzone, and 'walking' switching line. The design background, the rate measurement uncertainties, and the design solution are documented.
Martin, M. W.↗
Optical Firmware
Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.
Bergman, Larry A.↗
Counterrotator And Correlator For GPS Receivers
Accurate, all-digital, high-speed processor comprising correlator and down-converter developed for receivers in Global Positioning System (GPS). Processor reduces roundoff and commensurability errors to extremely small values. Use of digital chip and phase advancers provides outstanding control and accuracy in phase and feedback. Great flexibility imparted by provision for arbitrary starting time and integration length. Minimum-bit design requires minimum number of logical elements, thereby reducing size, power, and cost.
Thomas, J. Brooks↗
DEVS representation of dynamical systems - Event-based intelligent control
It is shown how systems can be advantageously represented as discrete-event models by using DEVS (discrete-event system specification), a set-theoretic formalism. Such DEVS models provide a basis for the design of event-based logic control. In this control paradigm, the controller expects to receive confirming sensor responses to its control commands within definite time windows determined by its DEVS model of the system under control. The event-based contral paradigm is applied in advanced robotic and intelligent automation, showing how classical process control can be readily interfaced with rule-based symbolic reasoning systems.
Zeigler, Bernard P.↗
Orbit transfer vehicle engine technology program. Task B-6 high speed turbopump bearings
Bearing types were evaluated for use on the Orbit Transfer Vehicle (OTV) high pressure fuel pump. The high speed, high load, and long bearing life requirements dictated selection of hydrostatic bearings as the logical candidate for this engine. Design and fabrication of a bearing tester to evaluate these cryogenic hydrostatic bearings was then conducted. Detailed analysis, evaluation of bearing materials, and design of the hydrostatic bearings were completed resulting in fabrication of Carbon P5N and Kentanium hydrostatic bearings. Rotordynamic analyses determined the exact bearing geometry chosen. Instrumentation was evaluated and data acquisition methods were determined for monitoring shaft motion up to speeds in excess of 200,000 RPM in a cryogenic atmosphere. Fabrication of all hardware was completed, but assembly and testing was conducted outside of this contract.
Source record↗
GaAs VLSI for aerospace electronics
Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.
Larue, G.↗
Insulation Reformulation Development
The current Space Launch System (SLS) internal solid rocket motor insulation, polybenzimidazole acrylonitrile butadiene rubber (PBI-NBR), is a new insulation that replaced asbestos-based insulations found in Space Shuttle heritage solid rocket boosters. PBI-NBR has some outstanding characteristics such as an excellent thermal erosion resistance, low thermal conductivity, and low density. PBI-NBR also has some significant challenges associated with its use: Air entrainment/entrapment during manufacture and lay-up/cure and low mechanical properties such as tensile strength, modulus, and fracture toughness. This technology development attempted to overcome these challenges by testing various reformulated versions of booster insulation. The results suggest the SLS program should continue to investigate material alternatives for potential block upgrades or use an entirely new, more advanced booster. The experimental design was composed of a logic path that performs iterative formulation and testing in order to maximize the effort. A lab mixing baseline was developed and documented for the Rubber Laboratory in Bldg. 4602/Room 1178.
Chapman, Cynthia↗
Concept-based Analysis of Neural Networks via Vision-Language Models
The analysis of vision-based deep neural networks (DNNs) is highly desirable but it is very challenging due to the difficulty of expressing formal specifications for vision tasks and the lack of efficient verification procedures. In this paper, we propose to leverage emerging multimodal, vision-language, foundation models (VLMs) as a lens through which we can reason about vision models. VLMs have been trained on a large body of images accompanied by their textual description, and are thus implicitly aware of high-level, human-understandable concepts describing the images. We describe a logical specification language Con spec designed to facilitate writing specifications in terms of these concepts. To define and formally check Con spec specifications, we build a map between the internal representations of a given vision model and a VLM, leading to an efficient verification procedure of natural-language properties for vision models. We demonstrate our techniques on a ResNet-based classifier trained on the RIVAL-10 dataset using CLIP as the multimodal model.
Large Vision Language Models↗
Efficient G(sup 4)FET-Based Logic Circuits
A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.
Vatan, Farrokh↗
The Sizing and Optimization Language, (SOL): Computer language for design problems
The Sizing and Optimization Language, (SOL), a new high level, special purpose computer language was developed to expedite application of numerical optimization to design problems and to make the process less error prone. SOL utilizes the ADS optimization software and provides a clear, concise syntax for describing an optimization problem, the OPTIMIZE description, which closely parallels the mathematical description of the problem. SOL offers language statements which can be used to model a design mathematically, with subroutines or code logic, and with existing FORTRAN routines. In addition, SOL provides error checking and clear output of the optimization results. Because of these language features, SOL is best suited to model and optimize a design concept when the model consits of mathematical expressions written in SOL. For such cases, SOL's unique syntax and error checking can be fully utilized. SOL is presently available for DEC VAX/VMS systems. A SOL package is available which includes the SOL compiler, runtime library routines, and a SOL reference manual.
Lucas, Stephen H.↗
Sequence-invariant state machines
A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured (BTS) logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods.
Whitaker, Sterling R.↗
SODA Synthesizer: an Open-source, Multi-level, Modular, Extensible Compiler from High-level Frameworks to Silicon
The SODA Synthesizer is an open-source modular, end-to-end hardware compiler framework. The SODA frontend, developed in MLIR, performs system-level design, code partitioning, and high-level optimizations to prepare the specifications for the hardware synthesis. The backend is based on a state-of-the-art high-level synthesis tool, and generates the final hardware design. The backend can interface with logic synthesis tools for field programmable gate arrays or with commercial and open-source logic synthesis tools for application-specific integrated circuits. We discuss the opportunities and challenges in integrating with commercial and open-source tools both at the frontend and backend, and the unique opportunities that an open-source hardware design ecosystem provides.
Bohm Agostini, Nicolas↗