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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Fermionic quantum processing with programmable neutral atom arrays

Simulating the properties of many-body fermionic systems is an outstanding computational challenge relevant to material science, quantum chemistry, and particle physics.-5.4pc]Please note that the spelling of the following author names in the manuscript differs from the spelling provided in the article metadata: D. González-Cuadra, D. Bluvstein, M. Kalinowski, R. Kaubruegger, N. Maskara, P. Naldesi, T. V. Zache, A. M. Kaufman, M. D. Lukin, H. Pichler, B. Vermersch, Jun Ye, and P. Zoller. The spelling provided in the manuscript has been retained; please confirm. Although qubit-based quantum computers can potentially tackle this problem more efficiently than classical devices, encoding nonlocal fermionic statistics introduces an overhead in the required resources, limiting their applicability on near-term architectures. In this work, we present a fermionic quantum processor, where fermionic models are locally encoded in a fermionic register and simulated in a hardware-efficient manner using fermionic gates. We consider in particular fermionic atoms in programmable tweezer arrays and develop different protocols to implement nonlocal gates, guaranteeing Fermi statistics at the hardware level. We use this gate set, together with Rydberg-mediated interaction gates, to find efficient circuit decompositions for digital and variational quantum simulation algorithms, illustrated here for molecular energy estimation. Finally, we consider a combined fermion-qubit architecture, where both the motional and internal degrees of freedom of the atoms are harnessed to efficiently implement quantum phase estimation as well as to simulate lattice gauge theory dynamics.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS1966

FET comparator detects analog signal levels without loading analog device

FET comparator circuit detects discrete analog computer output levels without excessively loading the output amplifier of the computer. An FET common source amplifier is coupled by a differential amplifier to a bistable transistor flip-flop. This circuit provides a digital output for analog voltages above or below a predetermined level.

Wallace, H. L.↗
NASA NTRS1968

Digital cardiotachometer system Patent

Digital cardiotachometer incorporating circuit for measuring heartbeat rate of subject over predetermined portion of one minute also converting rate to beats per minute

Mitchell, V. M.↗
NASA NTRS1974

Surface electrical properties experiment, part 1

The work is reported which was performed on the Surface Electrical Properties Experiment Data Acquisition System. Areas discussed include: data handling and processing, installation and external signal application, operation of the equipment, and digital output. Detailed circuit descriptions are included.

Strangway, D. W.↗
NASA NTRS1979

Maximum-likelihood data decoder

Digital convolutional decoder circuit for data communication receiver employs Viterbi decoding algorithm to quickly and efficiently decode data on basis of "maximum likelihood" computations.

Alberda, M. E.↗
NASA NTRS1978

Phase-locked loops and their application

A collection of papers is presented on the characteristics and capabilities of phase-locked loops (PLLs), along with some applications of interest. The discussion covers basic theory (linear and nonlinear); acquisition; threshold; stability; frequency demodulation and detection; tracking; cycle slipping and loss of lock; phase-locked oscillators; operation and performance in the presence of noise; AGC, AFC, and APC circuits and systems; digital PLL; and applications and miscellaneous. With the rapid development of IC technology, PLLs are expected to be used widely in consumer electronics.

Lindsey, W. C.↗
NASA NTRS1980

Low power, compact charge coupled device signal processing system

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated.

Bosshart, P. W.↗
NASA NTRS1983

VLSI technology and applications

Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described. Applications to communications circuits are presented.

Schilling, D. L.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS1989

Gallium arsenide processing for gate array logic

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Cole, Eric D.↗
NASA NTRS1993

General-Purpose Driver For Arrays Of Photodetectors

Electronic system containing both digital and analog circuits supplies clock waveforms at frequencies up to 12 MHz and/or bias voltages in 16 output channels. Designed to provide low-noise driving signals for any of variety of arrays of photodetectors. Clock waveform and/or bias in each channel adjusted independently of others to suit requirements of specific array of detectors. System offers primary advantage (adjustability) of prior laboratory systems, but at cost, power, and size like those of prior dedicated, field-deployed systems.

Shu, Peter K.↗
NASA NTRS1990

CMOS output buffer wave shaper

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

Albertson, L.↗
NASA NTRS1996

Stackable Electronic Computer Modules And Interconnections

Design concept for multiprocessor computer system calls for digital electronic processing circuits of various functionalities contained within identically shaped and sized regular polygonal modules interconnected and stacked by use of rings around edges. Rings contain wide-band bus circuits configured to provide connections to adjacent modules in same layer of stack and/or to modules in different layers. Provides flexibility of configuration to implement any of large variety of designs.

Bolotin, Gary S.↗
NASA NTRS1998

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Stoica, Adrian↗